A pad router for the Monterey Silicon Compiler
By: Carlos Francisco Rexach
Contributors: Naval Postgraduate School (U.S.)
Publisher: Naval Postgraduate School
Published: 1988
Place of publication: Monterey, Calif
Language: eng
Number of pages: 173
Subjects: Electrical and computer engineering
Description: A two layer pad router is developed for the Monterey Silicon Compiler. Features include an improved pad placement routine that extracts information from the internal layout to minimize chip area and wiring lengths, and a track allocation algorithm that minimizes the use of polysilicon during net layout. The router's performance was compared to that of the MacPitt's Silicon Compiler with four distinct circuits. The Monterey pad router layouts were 5% to 25% faster, and 10% to 15% smaller than those produced by MacPitts. Keywords: VLSI design, MacPitts, Silicon compiler, CAD Tools, Pad router, Pad placement, Router, Theses. (kt)
Notes: Thesis Advisor(s): Kirk, Donald E.

"March 1988."

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 1988.

Includes bibliographical references (p. 168-171).

"Approved for public release, distribution unlimited"--Cover.

US Navy (USN) author.