Massively Parallel Microprocessor Systems
Publisher: PRRB Publishing
Published: 2012
Place of publication: Laurel, MD, USA
Format: ebbok, with POD copy available
Number of pages: 98
Description: By the 1990's, it was becoming increasingly obvious that Massively Parallel Microprocessor-based Systems (MPMS) were becoming significant new forces in the marketplace, as well as a design approach of great importance. 

There is no one good source that discusses the architecture of MPMS. No one text gives the overall view of MPMS as a design philosophy, as a market force, and as a technology driver. Thus, I took on the thankless task of putting together this set of information. It is important to realize that in a rapidly moving, trendy area such as MPMS, by the time information is published, it is probably obsolete. By the time a book is published, it is probably only of historical significance. 

This book is intended for the hardware or software practitioner to use as an introduction to the subject. It assumes that the reader know something about the internals of computer systems, architecture, and instruction execution. It would be relevant for an advanced undergraduate or graduate level course in computer design or architecture. It discusses the chip level of MPMS, and looks at the design trade-offs at the systems level.

This document covers the field of MPMS. This is a subset of the field of Massively Parallel Computers. Although this variety of computer has been around for a long time, it only started to make an impact on the computer industry in the 1990's, as an alternative to supercomputers.

The goal of this document is to give the reader an introductory look at the fundamentals of MPMS design, to allow the reader to understand the trade-offs, limitations, speed, cost, complexity, and architectures. The reader will be shown the history and the trends of the technology of this rapidly moving field. To achieve these goals, we'll review the basics and background of the technology, to understand where the trade-offs are. We'll then look at real-world design examples to see how the trade-offs were made. It is essential to realize that in MPMS technology, as in many cutting edge endeavors, there are no wrong answers in the marketplace, but a multitude of right ones. The wrong answers either never make it to the market, or don't last long there.

This is not a source for designers, because the level of detail presented is not sufficient. However, it will be useful for engineers and engineering managers that must make use of this technology in systems. They need to know the capabilities and limitations of this important field, to be able to apply the technology in their particular domains of expertise.

MPMS is a rapidly evolving field. Software has not begun to catch up with the processors. Good software tools to develop, debug, and maintain MPMS are just emerging. MPMS is becoming mainstream.

In many cases we'll see decisions made that were not influenced totally by the technological issues, but mainly by marketing considerations. To the design engineer, this is heresy, but in the cold, cruel world, this is economic survival. Some companies are the pioneers at the "bleeding edge" of technology development; others prefer to hold back and address mature markets. As Nolan Bushnell says, "The Pioneers are the ones with the arrows in them".
Table of contents: title: Acknowledgments; title: Background; title: Scope; title: Organizations; title: Taxonomy; title: Introduction; title: •	MPMS Basics; title: •	The fetch/execute cycle; title: •	Elements of a computer; title: •	MPMS Architectures; title: •	Interconnection of Elements; title: •	Shared Memory Systems; title: •	Distributed Memory Systems; title: •	MPMS characteristics in review; title: MPMS approaches; title: •	Where is the bottleneck?; title: •	The 1.1 Problem; title: •	SMP, Clusters, and Parallel processing; title: •	Processor - I/O balance; title: •	Rate balancing; title: •	MPMS concepts; title: •	What MPMS is good for; title: •	Performance limitations of conventional architectures; title: •	The Teraflop goal and the Petaflop Possibility; title: •	Architectural Approaches for performance; title: •	The Evolution of MPMS; title: Development and Debug; title: •	Tools for Parallel Architectures; title: •	Vectorizing Compilers; title: •	Parallelizing Compilers; title: •	PVM; title: •	Development Environments; title: •	Debugging tools for Parallel systems; title: •	Benchmarking; title: Commodity Chip level products; title: •	Transputer; title: •	Intel's i80860; title: •	Pentium (IA-32, IA-64); title: •	DEC Alpha; title: •	MIPS; title: •	PowerPC; title: •	iWarp; title: Interconnect; title: •	Topology of Interconnection of Elements; title: •	The Mesh; title: •	The Hypercube; title: •	Tree; title: •	Torus; title: •	Reconfigurable topologies; title: •	Statically Reconfigurable Systems; title: •	Dynamically Reconfigurable Systems; title: •	Shared Memory Systems; title: •	Distributed Memory Systems; title: •	Physical Interconnect; title: •	Fibre Channel; title: •	SCSI-II; title: •	HIPPI; title: •	ATM; title: Issues in Mass Storage; title: •	DASD; title: •	RAID; title: •	Mass Store; title: •	Backup; title: Systems & Projects; title: •	Transtech; title: •	Meiko; title: •	Intel SSD; title: •	Mercury Computer Systems; title: •	Sky Computers; title: •	nCube; title: •	Tera Computer; title: •	Maspar; title: •	Pyramid; title: •	DEC; title: •	Cray T3D; title: •	NEC; title: •	KSR; title: •	Parsytec; title: •	Thinking Machines Corp.; title: •	Cray Superservers; title: •	IBM; title: •	Convex; title: •	Tandem; title: •	Unisys; title: •	Sun; title: •	SGI; title: •	GigaMachine; title: •	Loyola's 64 Node Parallel Processor; title: •	Beowolf Project; title: Glossary; title: General Bibliography; title: Bibliography on the Transputer; title: MPMS in Japan; title: Spacecraft Supercomputer; title: Trademarks