Logic synthesis and verification algorithms
By: by Gary D. Hachtel, Fabio Somenzi.
Contributors: Somenzi, Fabio.
Publisher: Kluwer Academic Publishers
Published: 1996
Place of publication: Boston
Language: eng
Number of pages: 564
Subjects: Integrated circuits -- Very large scale integration -- Design -- Data processing.; Logic design -- Data processing.; Integrated circuits -- Verification.; Computer-aided design.
Description: Logic Synthesis and Verification Algorithms blends mathematical foundations and algorithmic developments with circuit design issues. Each new technique is presented in the context of its application to design. Through the study of optimal two-level and multilevel combinational circuit design, the reader is introduced to basic concepts, such as Boolean algebra, local search, and algebraic factorization.

Similarly, through the study of optimal sequential circuit design, the reader is introduced to graph algorithms, finite state systems, and language theory. Throughout the book, recurrent themes such as branch and bound, dynamic programming, and symbolic implicit enumeration are used to establish optimal design principles.

Circuit designers and CAD tool developers alike will find Logic Synthesis and Verification Algorithms useful as an introductory and reference text. The rich collection of examples and solved problems make this book ideal for self study. Because of its careful balance of theory and application, Logic Synthesis and Verification Algorithms will serve well as a textbook for upper division and first year graduate students in electrical and computer engineering.
Notes: Includes bibliographical references (p. 537-553) and index.