Multi-core cache hierarchies
By: Rajeev Balasubramonian, Norman Jouppi, Naveen Muralimanohar
Contributors: Jouppi, Norman P. (Norman Paul); Muralimanohar, Naveen
Series: Synthesis lectures on computer architecture -- # 17
Publisher: Morgan & Claypool
Published: 2011
Place of publication: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA)
Language: eng
Format: [electronic resource] /
ISBN-13: 9781598297546; 9781598297539
Subjects: Computer architecture; Cache memory
Other titles: Synthesis digital library of engineering and computer science.
Description: A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever higher bandwidth demands on the memory system. All these issues make it important to avoid off-chip memory access by improving the efficiency of the on-chip cache. Future multi-core processors will have many large cache banks connected by a network and shared by many cores. Hence, many important problems must be solved: cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, difficulties in scaling existing technologies require adapting to and exploiting new technology constraints. The book attempts a synthesis of recent cache research that has focused on innovations for multi-core processors. It is an excellent starting point for early-stage graduate students, researchers, practitioners who wish to understand the landscape of recent cache research. The book is suitable as a reference for advanced computer architecture classes as well as for experienced researchers and VLSI engineers.
Notes: Part of: Synthesis digital library of engineering and computer science.

Series from website.

Includes bibliographical references (p. 119-136).

Abstract freely available; full-text restricted to subscribers or individual document purchasers.

Also available in print.

Mode of access: World Wide Web.

System requirements: Adobe Acrobat Reader.
Table of contents: title: Preface; title: Acknowledgments; title: 1. Basic elements of large cache design; title: Shared vs. private caches; title: Shared LLC; title: Private LLC; title: Workload analysis; title: Centralized vs. distributed shared caches; title: Non-uniform cache access; title: Inclusion; title: 2. Organizing data in CMP last level caches; title: Data management for a large shared NUCA cache; title: Placement/migration/search policies for D-NUCA; title: Replication policies in shared caches; title: OS-based page placement; title: Data management for a collection of private caches; title: Discussion; title: 3. Policies impacting cache hit rates; title: Cache partitioning for throughput and quality-of-service; title: Introduction; title: Throughput; title: QoS policies; title: Selecting a highly useful population for a large shared cache; title: Replacement/insertion policies; title: Novel organizations for associativity; title: Block-level optimizations; title: Summary; title: 4. Interconnection networks within large caches; title: Basic large cache design; title: Cache array design; title: Cache interconnects; title: Packet-switched routed networks; title: The impact of interconnect design on NUCA and UCA caches; title: NUCA caches; title: UCA caches; title: Innovative network architectures for large caches; title: 5. Technology; title: Static-RAM limitations; title: Parameter variation; title: Modeling methodology; title: Mitigating the effects of process variation; title: Tolerating hard and soft errors; title: Leveraging 3D stacking to resolve SRAM problems; title: Emerging technologies; title: 3T1D RAM; title: Embedded DRAM; title: Non-volatile memories; title: 6. Concluding remarks; title: Bibliography; title: Authors' biographies.