Context-flow system-on-chip platforms.
Published: 2004
Language: eng
Number of pages: 92
Description: Recent evolution in system-on-chip (SOC) design methodology demonstrates an important omission of a design principle that directly contributes to the success of conventional computer systems: the use of a simple programming model to separate application from architecture. In an effort to restore the powerful concept of programming in the context of system-on-chip, in this work we propose a new programming model, called context-flow, that is general-purpose, simple, safe, highly parallelizable yet transparent to the underlying architectural details. A high-performance SOC platform architecture is then designed to support this programming model, while fully exploiting the physical proximity between the processing elements. Using an architectural exploration framework with a multi-processor simulator, our case studies on real life applications demonstrate the feasibility of adapting imperative C programs to context-flow programs, as well as the performance efficiency of our context-flow architecture over bus-based and packet-switch-based alternatives. Finally, we propose an analytical performance model, based on queueing networks, for the new SOC platform architecture that is simple, synthesis-friendly, and as flexible and powerful as queueing theory.
Notes: Adviser:  Jianwen Zhu.

Thesis (M.A.Sc.)--University of Toronto, 2004.

Electronic version licensed for access by U. of T. users.

Source: Masters Abstracts International, Volume: 42-06, page: 2224.

MICR copy on microfiche (2 microfiches).