Asynchronous pulse logic
By: Mika Nyström, Alain J. Martin.
Contributors: Martin, Alain J.
Publisher: Kluwer Academic Publishers
Published: 2002
Place of publication: Boston
Language: eng
Number of pages: 206
Subjects: Electronic digital computers -- Circuits.; Asynchronous circuits.; Logic circuits.; Pulse circuits.
Description: "Asynchronous Pulse Logic is a comprehensive analysis of a newly developed asynchronous circuit family. The book covers circuit theory, practical circuits, design tools and an example of the design of a simple asynchronous microprocessor using the circuit family.".

"Asynchronous Pulse Logic will be of interest to the industrial and academic researcher working on high-speed VLSI systems. Graduate students will find this a useful reference for computer-aided design of asynchronous or related VLSI systems."--BOOK JACKET.
Notes: Includes bibliographical references (p. [195]-200) and index.
Table of contents: title: Machine generated contents note: 1. PRELIMINARIES; title: 1 High-speed CMOS-circuits; title: 2 Asynchronous protocols and delay-insensitive codes; title: 3 Production rules; title: 4 The MiniMIPS processor; title: 5 Commonly used abbreviations; title: 2. ASYNCHRONOUS-PULSE-LOGIC BASICS; title: 1 Road map of this chapter; title: 2 The pulse repeater; title: 2.1 Timing constraints in the pulse repeater; title: 2.2 Simulating the pulse repeater; title: 2.3 The synchronous digital model; title: 2.4 Asymmetric pulse-repeaters; title: 3 Formal model of pulse repeater; title: 3.1 Basic definitions; title: 3.2 Handling the practical simulations; title: 3.3 Expanding the model; title: 3.4 Using the extended model; title: 3.5 Noise margins; title: 4 Differential-equations treatment of pulse repeater; title: 4.1 Input behavior of pulse repeater; title: 3. COMPUTING WITH PULSES; title: I A simple logic example; title: 2 Pulse-handshake duty-cycle; title: 3 Single-track-handshake interfaces; title: 4 Timing constraints and timing "assumptions"; title: 5 Minimum cycle-transition-counts; title: 6 Solutions to transition-count problem; title: 7 The APL design-style in short; title: 4. A SINGLE-TRACK ASYNCHRONOUS-PULSE-; title: LOGIC FAMILY: I. BASIC CIRCUITS; title: 1 Preliminaries; title: 1.1 Transition counting in pipelined asynchronous circuits; title: 1.2 Transition-count choices in pulsed circuits; title: 1.3 Execution model; title: 1.4 Capabilities of the STAPL family; title: 1.5 Design philosophy; title: 2 The basic template; title: 2.1 Bit generator; title: 2.2 Bit bucket; title: 2.3 Left-right buffer; title: 3 Summary of properties of the simple circuits; title: 5. A SINGLE-TRACK ASYNCHRONOUS-PULSE-; title: LOGIC FAMILY: II. ADVANCED CIRCUITS; title: 1 Multiple input and output channels; title: 1.1 Naive implementation; title: 1.2 Double triggering of logic block in the naive design; title: 1.3 Solution; title: 1.4 Timing assumptions; title: 2 General logic computations; title: 2.1 Inputs whose values are not used; title: 3 Conditional communications; title: 3.1 The same program can be expressed in several ways; title: 3.2 Simple techniques for sends; title: 3.3 General techniques for conditional communications; title: 4 Storing state; title: 4.1 The general state-storing problem; title: 4.2 Implementing state variables; title: 4.3 Compiling the state bit; title: 5 Special circuits; title: 5.1 Arbitration; title: 5.2 Four-phase converters; title: 6 Resetting STAPL circuits; title: 6.1 Previously used resetting schemes; title: 6.2 An example; title: 6.3 Generating initial tokens; title: 7 How our circuits relate to the design philosophy; title: 8 Noise; title: 8.1 External noise-sources; title: 8.2 Charge sharing; title: 8.3 Crosstalk; title: 8.4 Design inaccuracies; title: 6. AUTOMATIC GENERATION OF; title: ASYNCHRONOUS-PULSE-LOGIC CIRCUITS; title: 1 Straightforwardly compiling from a higher-level specification; title: 2 An alternative compilation method; title: 3 What we compile; title: 4 The PL1 language; title: 4.1 Channels or shared variables?; title: 4.2 Simple description of the PL1 language; title: 4.3 An example: the replicator; title: 5 Compiling PLI; title: 6 PL 1-compiler front-end; title: 6.1 Determinism conditions; title: 6.2 Data encoding; title: 7 PL -compiler back-end; title: 7.1 Slack; title: 7.2 Logic simplification; title: 7.3 Code generation; title: 7. A DESIGN EXAMPLE:; title: THE SPAM MICROPROCESSOR; title: 1 The SPAM architecture; title: 2 SPAM implementation; title: 2.1 Decomposition; title: 2.2 Arbitrated branch-delay; title: 2.3 Byte skewing; title: 3 Design examples; title: 3.1 The PCUNIT; title: 3.2 The REGFILE; title: 4 Performance measurements on the SPAM implementation; title: 4.1 Straightline program; title: 4.2 Computing Fibonacci numbers; title: 4.3 Energy measurements; title: 4.4 Summary of SPAM implementation's performance; title: 4.5 Comparison with QDI; title: 8. RELATED WORK; title: 1 Theory; title: 2 STAPL circuit family; title: 3 PL1 language; title: 4 SPAM microprocessor; title: 9. LESSONS LEARNED; title: 1 Conclusion; title: Appendices; title: PL1 Report; title: 0.1 Scope; title: 0.2 Structure of PL1; title: 1 Syntax elements; title: 1.1 Keywords; title: 1.2 Comments; title: 1.3 Numericals; title: 1.4 Identifiers; title: 1.5 Reserved special operators; title: 1.6 Expression operators; title: 1.7 Expression syntax; title: 1.8 Actions; title: 2 PL1 process description; title: 2.1 Declarations; title: 2.2 Communication statement; title: 2.3 Process communication-block; title: 3 Semantics; title: 3.1 Expression semantics; title: 3.2 Action semantics; title: 3.3 Execution semantics; title: 3.4 Invariants; title: 3.5 Semantics in terms of CHP; title: 3.6 Slack elasticity; title: 4 Examples; title: SPAM Processor Architecture Definition; title: 1 SPAM overview; title: 2 SPAM instruction format; title: 3 SPAM instruction semantics; title: 3.1 Operand generation; title: 3.2 Operation definitions; title: 4 Assembly-language conventions; title: 4.1 The SPAM assembly format; title: Proof that Definition 2.2 Defines a Partial Order; title: 1 Remark on Continuity.