A primer on memory consistency and cache coherence
By: Daniel J. Sorin, Mark D. Hill, David A. Wood
Contributors: Hill, Mark D. (Mark Donald); Wood, David A.
Series: Synthesis lectures on computer architecture -- # 16
Publisher: Morgan & Claypool
Published: 2011
Place of publication: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA)
Language: eng
Format: [electronic resource] /
ISBN-13: 9781608455652; 9781608455645
Subjects: Memory management (Computer science); Distributed shared memory; Cache memory
Other titles: Synthesis digital library of engineering and computer science.
Description: Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high level concepts as well as specific, concrete examples from real-world systems.
Notes: Part of: Synthesis digital library of engineering and computer science.

Series from website.

Includes bibliographical references.

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Table of contents: title: Preface; title: 1. Introduction to consistency and coherence; title: Consistency (a.k.a., memory consistency, memory consistency model or memory model); title: Coherence (a.k.a., cache coherence); title: A consistency and coherence quiz; title: What this primer does not do; title: 2. Coherence basics; title: Baseline system model; title: The problem: how incoherence could possibly occur; title: Defining coherence; title: Maintaining the coherence invariants; title: The granularity of coherence; title: The scope of coherence; title: References; title: 3. Memory consistency motivation and sequential consistency; title: Problems with shared memory behavior; title: What is a memory consistency model; title: Consistency vs. coherence; title: Basic idea of sequential consistency (SC); title: A little SC formalism; title: Naive SC implementations; title: A basic SC implementation with cache coherence; title: Optimized SC implementations with cache coherence; title: Atomic operations with SC; title: Putting it all together: MIPS R10000; title: Further reading regarding SC; title: References; title: 4. Total store order and the x86 memory model; title: Motivation for TSO/x86; title: Basic idea of TSO/x86; title: A little TSO formalism and an x86 conjecture; title: Implementing TSO/x86; title: Atomic instructions and fences with TSO; title: Atomic instructions; title: Fences; title: Further reading regarding TSO; title: Comparing SC and TSO; title: References; title: 5. Relaxed memory consistency; title: Motivation; title: Opportunities to reorder memory operations; title: Opportunities to exploit reordering; title: An example relaxed consistency model (XC); title: The basic idea of the XC model; title: Examples using fences under XC; title: Formalizing XC; title: Examples showing XC operating correctly; title: Implementing XC; title: Atomic instructions with XC; title: Fences with XC; title: A caveat; title: Sequential consistency for data-race-free programs; title: Some relaxed model concepts; title: Release consistency; title: Causality and write atomicity; title: A relaxed memory model case study: IBM power; title: Further reading and commercial relaxed memory models; title: Academic literature; title: Commercial models; title: Comparing memory models; title: How do relaxed memory models relate to each other and TSO and SC; title: How good are relaxed models; title: High-level language models; title: References; title: 6. Coherence protocols; title: The big picture; title: Specifying coherence protocols; title: Example of a simple coherence protocol; title: Overview of coherence protocol design space; title: States; title: Transactions; title: Major protocol design options; title: References; title: 7. Snooping coherence protocols; title: Introduction to snooping; title: Baseline snooping protocol; title: High-level protocol specification; title: Simple snooping system model: atomic requests; title: Atomic transactions; title: Baseline snooping system model: non-atomic requests, atomic transactions; title: Running example; title: Protocol simplifications; title: Adding the exclusive state; title: Motivation; title: Getting to the exclusive state; title: High-level specification of protocol; title: Detailed specification; title: Running example; title: Adding the owned state; title: Motivation; title: High-level protocol specification; title: Detailed protocol specification; title: Running example; title: Non-atomic bus; title: Motivation; title: In-order vs. out-of-order responses; title: Non-atomic system model; title: An MSI protocol with a split-transaction bus; title: An optimized, non-stalling MSI protocol with a split-transaction bus; title: Optimizations to the bus interconnection network; title: Separate non-bus network for data responses; title: Logical bus for coherence requests; title: Case studies; title: Sun Starfire E10000; title: IBM Power5; title: Discussion and the future of snooping; title: References; title: 8. Directory coherence protocols; title: Introduction to directory protocols; title: Baseline directory system; title: Directory system model; title: High-level protocol specification; title: Avoiding deadlock; title: Detailed protocol specification; title: Protocol operation; title: Protocol simplifications; title: Adding the exclusive state; title: High-level protocol specification; title: Detailed protocol specification; title: Adding the owned state; title: High-level protocol specification; title: Detailed protocol specification; title: Representing directory state; title: Coarse directory; title: Limited pointer directory; title: Directory organization; title: Directory cache backed by DRAM; title: Inclusive directory caches; title: Null directory cache (with no backing store); title: Performance and scalability optimizations; title: Distributed directories; title: Non-stalling directory protocols; title: Interconnection networks without point-to-point ordering; title: Silent vs. non-silent evictions of blocks in state S; title: Case studies; title: SGI origin 2000; title: Coherent hypertransport; title: Hypertransport assist; title: Intel QPI; title: Discussion and the future of directory protocols; title: References; title: 9. Advanced topics in coherence; title: System models; title: Instruction caches; title: Translation lookaside buffers (TLBS); title: Virtual caches; title: Write-through caches; title: Coherent direct memory access (DMA); title: Multi-level caches and hierarchical coherence protocols; title: Performance optimizations; title: Migratory sharing optimization; title: False sharing optimizations; title: Maintaining liveness; title: Deadlock; title: Livelock; title: Starvation; title: Token coherence; title: The future of coherence; title: References; title: Author biographies.