A practical guide to adopting the Universal Verification Methodology (UVM)
By: Sharon Rosenberg, Kathleen A. Meade
Contributors: Meade, Kathleen A.
Series: UVM
Publisher: Cadence Design Systems
Published: 2010
Place of publication: San Jose, CA
Language: eng
Number of pages: 275
ISBN-13: 9780578059556; 9780578059956
Subjects: Debugging in computer science; Computer software; Verification; Computer programs
Notes: Includes index.
Table of contents: title: Preface
pagenum: xvii; label: 1
title: What is the Universal Verification Methodology (UVM)?
pagenum: 1; label: 1.1
title: Verification Planning and Coverage-Driven Verification
pagenum: 2; label: 1.2
title: Multi-Language and Methodologies
pagenum: 4; label: 1.3
title: What is Unique about This Book?
pagenum: 4; label: 1.4
title: How to Use This Book
pagenum: 4; label: 1.4.1
title: How to Run the Examples
pagenum: 5; label: 1.4.2
title: Conventions in This Book
pagenum: 6; label: 1.4.3
title: Abbreviations
pagenum: 7; label: 2
title: UVM Overview
pagenum: 9; label: 2.1
title: UVM Testbench and Environments
pagenum: 9; label: 2.2
title: Interface UVCs
pagenum: 11; label: 2.3
title: System and Module UVCs
pagenum: 14; label: 2.3.1
title: Software UVCs
pagenum: 15; label: 2.4
title: The SystemVerilog UVM Class Library
pagenum: 16; label: 2.4.1
title: UVM Utilities
pagenum: 18; label: 3
title: Object-Oriented Programming (OOP)
pagenum: 21; label: 3.1
title: Introduction
pagenum: 21; label: 3.2
title: Designing Large Software Applications
pagenum: 22; label: 3.3
title: What is an Object in OOP?
pagenum: 22; label: 3.4
title: Distributed Development Environment
pagenum: 22; label: 3.5
title: Separation of Concerns
pagenum: 23; label: 3.6
title: Classes, Objects, and Programs
pagenum: 23; label: 3.7
title: Using Generalization and Inheritance
pagenum: 24; label: 3.8
title: Creating Compact Reusable Code
pagenum: 26; label: 3.9
title: Polymorphism in OOP
pagenum: 26; label: 3.10
title: Downcast
pagenum: 27; label: 3.11
title: Class Libraries
pagenum: 28; label: 3.12
title: Static Methods and Attributes
pagenum: 29; label: 3.13
title: Parameterized Classes
pagenum: 29; label: 3.14
title: Packages and Namespaces
pagenum: 30; label: 3.15
title: Unified Modeling-Language Diagrams
pagenum: 31; label: 3.16
title: Software Design Patterns
pagenum: 32; label: 3.16.1
title: Software Design Anti-Patterns
pagenum: 33; label: 3.17
title: Why Isn't the Existing OOP Methodology Enough?
pagenum: 33; label: 3.18
title: Aspect-Oriented Programming
pagenum: 34; label: 4
title: UVM Library Basics
pagenum: 35; label: 4.1
title: Using the UVM Library
pagenum: 35; label: 4.1.1
title: Hello World Example
pagenum: 36; label: 4.1.2
title: Guidelines for Using the UVM Library
pagenum: 36; label: 4.2
title: Library Base Classes
pagenum: 37; label: 4.3
title: The uvm_object Class
pagenum: 37; label: 4.3.1
title: UVM Field Automation
pagenum: 39; label: 4.3.2
title: uvm_object Definition Guidelines
pagenum: 39; label: 4.3.3
title: UVM Object Automation Usage Examples
pagenum: 41; label: 4.3.4
title: Using UVM Field Automation
pagenum: 42; label: 4.4
title: The uvm_component Class
pagenum: 43; label: 4.4.1
title: Simulation Phase Methods
pagenum: 43; label: 4.4.2
title: Hierarchy Information Functions
pagenum: 46; label: 4.4.3
title: uvm_top Component
pagenum: 49; label: 4.5
title: UVM Configuration Mechanism
pagenum: 49; label: 4.6
title: Transaction-Level Modeling in UVM
pagenum: 52; label: 4.6.1
title: Key TLM Concepts in UVM
pagenum: 53; label: 4.7
title: UVM Factory
pagenum: 62; label: 4.8
title: UVM Message Facilities
pagenum: 66; label: 4.8.1
title: UVM Message APIs
pagenum: 66; label: 4.8.2
title: Guidelines for Using UVM Messages
pagenum: 67; label: 4.8.3
title: Modifying Message Verbosity
pagenum: 67; label: 4.9
title: Callbacks
pagenum: 68; label: 4.9.1
title: Using Callbacks
pagenum: 68; label: 4.9.2
title: Guidelines for Using Callbacks
pagenum: 70; label: 4.9.3
title: The Report Catcher Built-In Callback
pagenum: 71; label: 5
title: Interface UVCs
pagenum: 73; label: 5.1
title: Stimulus Modeling and Generation
pagenum: 73; label: 5.1.1
title: Modeling Data Items
pagenum: 73; label: 5.1.2
title: Defining Control Fields
pagenum: 75; label: 5.1.3
title: Inheritance and Constraint Layering
pagenum: 76; label: 5.1.4
title: Using Empty Constraint Blocks for Tests
pagenum: 77; label: 5.1.5
title: A Simple Data Item Test
pagenum: 77; label: 5.2
title: Creating the Driver
pagenum: 78; label: 5.2.1
title: The SystemVerilog Interface and Virtual Interface
pagenum: 80; label: 5.3
title: Creating the Sequencer
pagenum: 82; label: 5.3.1
title: Key Randomization Requirements
pagenum: 82; label: 5.3.2
title: A Non-UVM Generator
pagenum: 83; label: 5.3.3
title: The UVM Sequencer
pagenum: 85; label: 5.4
title: Connecting the Driver and Sequencer
pagenum: 86; label: 5.4.1
title: Basic Sequencer and Driver Interaction
pagenum: 87; label: 5.4.2
title: Querying for the Randomized Item
pagenum: 87; label: 5.4.3
title: Supporting Pipeline Protocols
pagenum: 88; label: 5.4.4
title: Sending Processed Data Back to the Sequencer
pagenum: 89; label: 5.5
title: Creating the Collector and Monitor
pagenum: 89; label: 5.5.1
title: Connecting the Collector and Monitor
pagenum: 93; label: 5.6
title: Modeling Topology with UVM
pagenum: 93; label: 5.7
title: Creating the Agent
pagenum: 96; label: 5.7.1
title: Using connect() to Connect Components
pagenum: 99; label: 5.7.2
title: Agent Configuration
pagenum: 99; label: 5.8
title: Creating the UVM Verification Component
pagenum: 99; label: 5.8.1
title: The Environment Class
pagenum: 100; label: 5.8.2
title: Point-to-Point Environments
pagenum: 102; label: 5.8.3
title: The UVM Configuration Mechanism
pagenum: 103; label: 5.8.4
title: Setting the Agent Virtual Interface
pagenum: 107; label: 5.9
title: Creating UVM Sequences
pagenum: 110; label: 5.9.1
title: User-Defined Sequences
pagenum: 111; label: 5.9.2
title: Predefined Sequences
pagenum: 115; label: 5.10
title: Configuring the Sequencer's Default Sequence
pagenum: 116; label: 5.10.1
title: Controlling the Sequencer and Generated Sequences
pagenum: 117; label: 5.10.2
title: Overriding Sequence Items and Sequences
pagenum: 118; label: 5.10.3
title: Building a Reusable Sequence Library
pagenum: 118; label: 5.11
title: Coordinating End-of-Test
pagenum: 119; label: 5.11.1
title: UVM Objection Mechanism
pagenum: 119; label: 5.11.2
title: End-of-Test Objection Mechanism Usage
pagenum: 120; label: 5.11.3
title: Tracing Objection Information
pagenum: 121; label: 5.11.4
title: Setting Drain Time
pagenum: 122; label: 5.11.5
title: Identifying Lack of Progress
pagenum: 123; label: 5.12
title: Implementing Protocol-Specific Coverage and Checks
pagenum: 127; label: 5.12.1
title: Placing Coverage Groups
pagenum: 127; label: 5.12.2
title: Implementing Checks
pagenum: 129; label: 5.12.3
title: Enabling and Disabling Coverage and Checks
pagenum: 130; label: 5.12.4
title: Implementing Checks and Coverage in Interfaces
pagenum: 131; label: 5.13
title: Handling Reset
pagenum: 132; label: 5.13.1
title: Reset Methodology for Interface UVCs
pagenum: 132; label: 5.14
title: Packaging Interface UVCs
pagenum: 135; label: 5.14.1
title: Interface UVC Directory Structure
pagenum: 135; label: 5.14.2
title: File Naming Conventions
pagenum: 136; label: 5.14.3
title: UVC Packages
pagenum: 136; label: 6
title: Automating UVC Creation
pagenum: 139; label: 6.1
title: UVC Development Flow
pagenum: 139; label: 6.2
title: Code Generators
pagenum: 141; label: 6.3
title: Compliance Checklist
pagenum: 144; label: 6.4
title: Automated Compliance Checking
pagenum: 145; label: 7
title: Simple Testbench Integration
pagenum: 147; label: 7.1
title: Testbenches and Tests
pagenum: 147; label: 7.1.1
title: The Testbench Class
pagenum: 148; label: 7.1.2
title: The Test Classes
pagenum: 148; label: 7.2
title: Creating a Simple Testbench
pagenum: 149; label: 7.2.1
title: Instantiating UVCs in a Testbench
pagenum: 150; label: 7.3
title: Testbench Configuration
pagenum: 153; label: 7.3.1
title: UVC Configurable Parameters
pagenum: 153; label: 7.3.2
title: UVC Configuration Mechanism
pagenum: 153; label: 7.3.3
title: Using a Configuration Class
pagenum: 154; label: 7.4
title: Creating a Test
pagenum: 156; label: 7.4.1
title: Creating the Base Test
pagenum: 156; label: 7.4.2
title: Creating a Test Library Using a Base Test
pagenum: 157; label: 7.4.3
title: Test Selection
pagenum: 157; label: 7.5
title: Creating Meaningful Tests
pagenum: 158; label: 7.5.1
title: Constraining Data Items
pagenum: 158; label: 7.5.2
title: Sequences and Sequencer Control
pagenum: 161; label: 7.6
title: Virtual Sequencers and Sequences
pagenum: 167; label: 7.6.1
title: The Virtual Sequencer
pagenum: 168; label: 7.6.2
title: Creating a Virtual Sequence
pagenum: 169; label: 7.6.3
title: Controlling Other Sequencers
pagenum: 170; label: 7.6.4
title: Connecting a Virtual Sequencer to Sub-Sequencers
pagenum: 171; label: 7.7
title: Checking for DUT Correctness
pagenum: 172; label: 7.7.1
title: Scoreboards
pagenum: 172; label: 7.8
title: Implementing a Coverage Model
pagenum: 175; label: 7.8.1
title: Selecting a Coverage Method
pagenum: 175; label: 7.8.2
title: Implementing a Functional Coverage Model
pagenum: 176; label: 8
title: Stimulus Generation Topics
pagenum: 177; label: 8.1
title: Fine Control Sequence Generation
pagenum: 177; label: 8.2
title: Executing Multiple Sequences Concurrently
pagenum: 180; label: 8.2.1
title: Using fork/join and `uvm_do` in the Body of a Sequence
pagenum: 180; label: 8.2.2
title: Starting Several Sequences in Parallel
pagenum: 180; label: 8.3
title: Using p_sequencer
pagenum: 181; label: 8.4
title: Using the pre_body() and post_body() Methods
pagenum: 181; label: 8.5
title: Controlling the Arbitration of Items
pagenum: 182; label: 8.6
title: Interrupt Sequences
pagenum: 183; label: 8.7
title: Protocol Layering
pagenum: 184; label: 8.7.1
title: Layering of Protocols
pagenum: 185; label: 8.7.2
title: Layering and Sequences
pagenum: 185; label: 8.7.3
title: Styles of Layering
pagenum: 188; label: 8.7.4
title: Using Layered Sequencers
pagenum: 192; label: 9
title: Register and Memory Package
pagenum: 197; label: 9.1
title: Register-Related Terminology
pagenum: 198; label: 9.2
title: Register Package Overview
pagenum: 198; label: 9.2.1
title: Register Packages Usage Flow
pagenum: 199; label: 9.2.2
title: uvm_rgm Hook-Up and Data Flow
pagenum: 199; label: 9.2.3
title: The Register Database (RGM_DB)
pagenum: 200; label: 9.2.4
title: Randomization and Injection
pagenum: 201; label: 9.2.5
title: Monitoring
pagenum: 201; label: 9.3
title: Using the uvm_rgm Package
pagenum: 202; label: 9.3.1
title: Defining the Register and Memory Models
pagenum: 202; label: 9.3.2
title: Creating an IP-XACT File
pagenum: 202; label: 9.3.3
title: Creating uvm_rgm SystemVerilog Classes
pagenum: 204; label: 9.4
title: Connecting uvm_rgm Components in a Testbench
pagenum: 210; label: 9.4.1
title: Connecting Register Components to a Testbench
pagenum: 210; label: 9.4.2
title: Adding the Necessary Infrastructure to the Bus Master Sequencer
pagenum: 211; label: 9.4.3
title: Instantiation and Connection to the Testbench
pagenum: 214; label: 9.4.4
title: Reset Handling
pagenum: 217; label: 9.5
title: Controlling Register Scenarios
pagenum: 217; label: 9.5.1
title: Register Operations
pagenum: 218; label: 9.5.2
title: Register Read/Write Sequences
pagenum: 219; label: 9.5.3
title: Multi-Register Sequence Operations
pagenum: 221; label: 9.5.4
title: Sequences Reuse
pagenum: 222; label: 9.6
title: Using uvm_rgm for Checking
pagenum: 222; label: 9.6.1
title: Using the Shadow Model for Checking
pagenum: 222; label: 9.6.2
title: Advanced Register Checking
pagenum: 222; label: 9.7
title: Updating the Register Database Model
pagenum: 223; label: 9.7.1
title: Updating the Module UVC
pagenum: 224; label: 9.8
title: Collecting Coverage of Register Activities
pagenum: 225; label: 9.8.1
title: Using uvm_rgm Automatic Coverage Facilities
pagenum: 225; label: 9.8.2
title: User-Defined Coverage
pagenum: 226; label: 9.9
title: Controlling Coverage-Sampling Time
pagenum: 227; label: 10
title: System UVCs and Testbench Integration
pagenum: 229; label: 10.1
title: Introduction
pagenum: 229; label: 10.2
title: Module and System UVC Architecture
pagenum: 231; label: 10.2.1
title: Reuse in Module and System UVCs
pagenum: 231; label: 10.2.2
title: Module UVC Architecture
pagenum: 232; label: 10.2.3
title: System UVC Architecture
pagenum: 233; label: 10.3
title: Sub-Components of Module and System UVCs
pagenum: 234; label: 10.3.1
title: Monitor
pagenum: 234; label: 10.3.2
title: Memory Blocks and Register Files
pagenum: 237; label: 10.3.3
title: Active Stand-In Mode
pagenum: 237; label: 10.3.4
title: The Module UVC Class
pagenum: 238; label: 10.4
title: Module UVC Configuration
pagenum: 238; label: 10.4.1
title: Standard Configuration Modes
pagenum: 239; label: 10.4.2
title: Module UVC Reconfiguration
pagenum: 240; label: 10.5
title: The Testbench
pagenum: 241; label: 10.5.1
title: The UART Controller Testbench Strategy
pagenum: 243; label: 10.5.2
title: Virtual Sequencer and Register Sequencer
pagenum: 246; label: 10.5.3
title: Interface UVC Extensions
pagenum: 246; label: 10.6
title: Sequences
pagenum: 246; label: 10.6.1
title: Developing Reusable Sequences
pagenum: 247; label: 10.7
title: Coverage
pagenum: 248; label: 10.7.1
title: Module UVC Coverage
pagenum: 249; label: 10.7.2
title: System-Level Coverage
pagenum: 252; label: 10.7.3
title: Adding Coverage Definitions to System UVCs
pagenum: 252; label: 10.8
title: Stand-In Mode
pagenum: 252; label: 10.9
title: Scalability Concerns in System Verification
pagenum: 254; label: 10.9.1
title: Randomization and Stimuli Creation
pagenum: 255; label: 10.9.2
title: Coverage
pagenum: 255; label: 10.9.3
title: Messages
pagenum: 256; label: 10.10
title: Module UVC Directory Structure
pagenum: 256; label: 11
title: The Future of UVM
pagenum: 259; label: 11.1
title: Commercial UVM Verification IP
pagenum: 259; label: 11.2
title: Class Library Enhancements
pagenum: 260; label: 11.2.1
title: Register Package
pagenum: 260; label: 11.2.2
title: Run-Time Phases
pagenum: 260; label: 11.2.3
title: Multi-Language Integration
pagenum: 261; label: 11.3
title: Multi-Domain UVM
pagenum: 263; title: The Authors
pagenum: 265; title: Index
pagenum: 267