Analog Device-Level Layout Automation
By: by John M. Cohn, David J. Garrod, Rob A. Rutenbar, L. Richard Carley
Contributors: Garrod, D. J. (David J.); Rutenbar, Rob A.; Carley, L. Richard
Series: The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing -- 263; Kluwer international series in engineering and computer science -- 263.
Publisher: Springer US
Published: 1994
Place of publication: Boston, MA
Language: eng
Format: [electronic resource] /
Number of pages: 285
ISBN-13: 9781461361893; 9781461527565
Subjects: Systems engineering; Engineering; Computer-aided design; Computer engineering
Description: This monograph addresses the problem of device layout for high-performance custom analog cells. In particular, an alternative placement and routing formulation is proposed that is designed to minimize the cost in layout quality that is traditionally associated with analog layout automation. The goal of analog layout is to minimize the effects of layout induced performance degradation while, at the same time, to maximize the area utilization of the circuit. Human layout experts observe a variety of analog-specific layout constraints and exploit a range of geometric optimizations to achieve these performance and density goals. This work is directed at discovering how these constraints and optimizations can best be incorporated into automatic layout optimization. Two of the products of this research are a new analog device-level placer, KOAN, and a new analog device-level router, ANAGRAM II [40], which incorporate a more comprehensive set of layout constraints and geometric optimizations than in any previous systems. Analog Device-Level Layout Automation focuses on the formulation, algorithms, and certain relevant implementation details of KOAN and ANAGRAM II.
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