Architecture of Computing Systems – ARCS 2013
Subtitle: 26th International Conference, Prague, Czech Republic, February 19-22, 2013. Proceedings
By: edited by Hana Kubátová, Christian Hochberger, Martin Daněk, Bernhard Sick
Contributors: Hochberger, Christian; Daněk, Martin; Sick, Bernhard; SpringerLink (Online service)
Series: Lecture Notes in Computer Science -- 7767
Publisher: Springer Berlin Heidelberg; Imprint: Springer
Published: 2013
Place of publication: Berlin, Heidelberg
Language: eng
Format: [electronic resource] :
Number of pages: 354
ISBN-13: 9783642364242
Subjects: Software engineering; Information organization; Information storage and retrieval systems; Computer network architectures; Information retrieval; Computer System Implementation; Computer Communication Networks; Information Systems Applications (incl. Internet); Computer science; Operating systems (Computers); Operating Systems
Description: This book constitutes the refereed proceedings of the 26th International Conference on Architecture of Computing Systems, ARCS 2013, held in Prague, Czech Republic, in February 2013.The 29 papers presented were carefully reviewed and selected from 73 submissions. The topics covered arecomputer architecture topics such as multi-cores, memory systems, and parallel computing, adaptive system architectures such as reconfigurable systems in hardware and software, customization and application specific accelerators in heterogeneous architectures, organic and autonomic computing including both theoretical and practical results on self-organization, self-configuration, self-optimization, self-healing, and self-protection techniques, operating systems including but not limited to scheduling, memory management, power management, RTOS, energy-awareness, and green computing.
Table of contents: title: An Unstructured Termination Detection Algorithm Using Gossip in Cloud Computing Environments; title: Power Monitoring for Mixed-Criticality on a Many-Core Platform; title: On Confident Task-Accurate Performance Estimation; title: Exploiting Thermal Coupling Information in MPSoC Dynamic Thermal Management; title: A Multi-core Memory Organization for 3-D DRAM as Main Memory; title: Synthetic Aperture Radar Data Processing on an FPGA Multi-core System; title: Virtual Register Renaming; title: Load-Adaptive Monitor-Driven Hardware for Preventing Embedded Real-Time Systems from Overloads Caused by Excessive Interrupt Rates; title: Producer-Consumer: The Programming Model for Future Many-Core Processors; title: A Highly Dependable Self-adaptive Mixed-Signal Multi-core System-on-Chip; title: Inter-warp Instruction Temporal Locality in Deep-Multithreaded GPUs; title: GALS-CMP: Chip-Multiprocessor for GALS Embedded Systems; title: HW/SW Tradeoffs for Dynamic Message Scheduling in Controller Area Network (CAN); title: ^; title: A Data-Driven Approach for Executing the CG Method on Reconfigurable High-Performance Systems; title: Custom Reconfigurable Architecture Based on Virtex 5 Lookup Tables; title: Profiling Energy Consumption of I/O Functions in Embedded Applications; title: An Application-Aware Cache Replacement Policy for Last-Level Caches; title: Deploying Hardware Locks to Improve Performance and Energy Efficiency of Hardware Transactional Memory; title: Self-adaptation for Mobile Robot Algorithms Using Organic Computing Principles; title: Self-virtualized CAN Controller for Multi-core Processors in Real-Time Applications; title: Shrinking L1 Instruction Caches to Improve Energy–Delay in SMT Embedded Processors; title: Arithmetic Unit for Computations in GF(p) with the Left-Shifting Multiplicative Inverse Algorithm; title: HW-OSQM: Reducing the Impact of Event Signaling by Hardware-Based Operating System Queue Manipulation; title: Comparison of GPU and FPGA Implementation of SVM Algorithm for Fast Image Segmentation; title: ^; title: ^^; title: Automatic Floorplanning and Interface Synthesis of Island Style Reconfigurable Systems with GoAhead; title: Separable 2D Convolution with Polymorphic Register Files; title: Architecture of a Parallel MOSFET Parameter Extraction System; title: Predictable Two-Level Bus Arbitration for Heterogeneous Task Sets.; title: ^^