First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Subtitle: MEMOCODE'03 : proceedings : 24-26 June 2003, Mont Saint-Michel, France
By: sponsored by IEEE Cpmputer Society Design Automation Technical Committee (DATC), IEEE Circuits and Systems Society, ACM Special Interest Group on Design Automation ; in cooperation with INRIA ; with financial support from IRISA, CNRS
Contributors: IEEE Computer Society. Design Automation Technical Committee; IEEE Circuits and Systems Society; ACM Special Interest Group on Design Automation
Publisher: IEEE Computer Society
Published: 2003
Place of publication: Los Alamitos, Calif
Language: eng
Number of pages: 285
Copyright date: 2003
Subjects: Computer simulation; Congresses
Other titles: MEMOCODE'03; Formal Methods and Models for Co-Design, 2003, MEMOCODE '03, proceedings, First ACM and IEEE International Conference on.
Notes: "IEEE Computer Society Order Number PR01923"--T.p. verso.

Includes bibliographical references and index.
Table of contents: title: Executable Computational Logics: Combining Formal Methods and Programming Language Based System Design  -- J. Meseguer; title: MoDe: A Method for System-Level Architecture Evaluation  -- J. Romberg, O. Slotosch and G. Hahn; title: From Use Cases to System Implementation: Statechart Based Co-design  -- L. Gomes and A. Costa; title: Petri Net Based Interface Analysis for Fast IP-Core Integration  -- J. Filho, M. de Lima and P. Maciel; title: Goal-Oriented Requirements Analysis for Process Control Systems Design  -- I. El-Maddah and T. Maibaum; title: Analyzing Concurrency in Computational Networks  -- S. Stuijk and T. Basten; title: Translating Fusion/UML to Object-Z  -- M. Bittner and F. Kammuller; title: Finding Good Counter-Examples to Aid Design Verification  -- G. Fey and R. Drechsler; title: High Level Verification for Control Intensive Systems Using Predicate Abstraction  -- E. Clarke, O. Grumberg, M. Talupur and D. Wang; title: Formal Verification of an Intel XScale Processor Model with Scoreboarding, Specialized Execution Pipelines, and Imprecise Data-Memory Exceptions  -- S. Srinivasan and M. Velev; title: Combining ACL2 and a [nu]-calculus Model-Checker to Verify System-Level Designs  -- M. Contensin and L. Pierre; title: Engineering Changes in Field Modifiable Architectures  -- H. Saito, K. Seto, Y. Kojima, S. Komatsu and M. Fujita; title: Hierarchical and Incremental Verification for System Level Design: Challenges and Accomplishments  -- Grant Martin and Sandeep Shukla; title: How to Compute the Refinement Relation for Parameterized Systems  -- F. Bellegarde, C. Charlet and O. Kouchnarenko; title: Using SSDE for USB2.0 Conformance Co-verification  -- T. Omnes, G. Postuma, J. Verhaegh, M. Boonen and N. Gatherer; title: From Algorithm and Architecture Specifications to Automatic Generation of Distributed Real-Time Executives: A Seamless Flow of Graphs Transformations  -- T. Grandpierre and Y. Sorel; title: Methods for Exploiting SAT Solvers in Unbounded Model Checking  -- K. McMillan; title: On the Use of a High-Level Fault Model to Check Properties Incompleteness  -- F. Fummi, G. Pravadelli, A. Fedeli, U. Rossi and F. Toto; title: Exact Runtime Analysis Using Automata-Based Symbolic Simulation  -- T. Schule and K. Schneider; title: Real-Time Property Preservation in Approximations of Timed Systems  -- J. Huang, J. Voeten and M. Geilen; title: Reliability Evaluation for Dependable Embedded System Specifications: An Approach Based on DSPN  -- S. Fernandes and P. Maciel; title: Modular Hierarchies of Models for Embedded Systems  -- M. Broy; title: Verification of Transaction-Level SystemC Models Using RTL Testbenches  -- R. Jindal and K. Jain; title: LOTOS Code Generation for Model Checking of STBus Based SoC: The STBus Interconnect  -- P. Wodey, G. Camarroque, F. Baray, R. Hersemeule and J.-P. Cousin; title: A Generalized Approach to Supervisor Synthesis  -- R. Ziller and K. Schneider; title: Optimizations for Faster Execution of Esterel Programs  -- D. Potop-Butucaru and R. de Simone; title: Bridging CSP and C++ with Selective Formalism and Executable Specifications  -- W. Gardner; title: Bluespec: A Language for Hardware Design, Simulation, Synthesis and Verification  -- Arvind; title: A Verification Methodology for Infinite-State Message Passing Systems  -- C. Sprenger and K. Worytkiewicz; title: Verification of Control Properties in the Polyhedral Model  -- D. Cachera and K. Morin-Allory; title: Should the Space of Implementation Possibilities Be Determined by the Abilities of High-Level Synthesis and Validation?  -- Rajesh Gupta and Sandeep Shukla; title: Robust System Design with Uncertain Information -- G. De Micheli.