Diagnosis of combinational logic circuits using Boolean satisfiability.
Published: 2004
Language: eng
Number of pages: 90
Description: Boolean satisfiability (SAT) solvers are being used to solve an increasing number of Electronic Design Automation (EDA) problems. This trend is largely due to significant advances in SAT solving algorithms in recent years. SAT has already been shown to be a powerful and flexible tool for solving many existing EDA problems. However, no SAT-based solution has yet been proposed for the problem of diagnosis. This thesis presents a novel SAT-based framework for performing diagnosis of combinational logic circuits. An algorithm is described which can be used for model-free design error and fault diagnosis, and for model-based fault diagnosis using several common fault models. Several heuristics are analysed that improve the runtime and reduce the memory requirements of the algorithm.
Notes: Adviser:  Andreas Veneris.

Thesis (M.A.Sc.)--University of Toronto, 2004.

Electronic version licensed for access by U. of T. users.

Source: Masters Abstracts International, Volume: 43-03, page: 0946.

MICR copy on microfiche (2 microfiches).

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