SPARC architecture, assembly language programming, and C
By: Richard P. Paul
Edition: 2nd ed.
Publisher: Prentice Hall
Published: 2000
Place of publication: Upper Saddle River, N.J
Language: eng
Number of pages: 505
ISBN-13: 9780130255969
Subjects: Reduced instruction set computers; Assembler language (Computer program language); C (Computer program language)
Notes: Includes bibliographical references (p. 489-491) and index.
Table of contents: title: 1; title: Computer -- 1 -- 1.2; title: Calculators -- 1 -- 1.2.1; title: Stack Calculators -- 2 -- 1.2.2; title: Use of Registers -- 4 -- 1.2.3; title: Programmable Calculators -- 6 -- 1.2.4; title: Machine Language Programming -- 8 -- 1.3; title: m4: The Macro Processor -- 9 -- 1.3.1; title: Macros with Arguments -- 10 -- 1.3.2; title: Memory Location -- 13 -- 1.3.3; title: Conditionals and Branching -- 14 -- 1.4; title: Von Neumann Machine -- 17 -- 1.5; title: Stack Machine -- 17 -- 1.6; title: Java Virtual Machine -- 20 -- 1.7; title: Accumulator Machines -- 30 -- 1.8; title: Load/Store Machines -- 33 -- 1.9; title: Assemblers -- 39 -- 2; title: Sparc Architecture -- 51 -- 2.2; title: Registers -- 51 -- 2.3; title: SPARC Assembly Language Programming -- 52 -- 2.5; title: Pipelining -- 56 -- 2.6; title: Example Continued -- 61 -- 2.7; title: Debugger gdb -- 63 -- 2.8; title: Filling Delay Slots -- 67 -- 2.9; title: Branching -- 70 -- 2.9.1; title: Testing -- 70 -- 2.9.2; title: Branches -- 71 -- 2.10; title: Control Statements -- 77 -- 2.10.1; title: While -- 78 -- 2.10.2; title: Do -- 80 -- 2.10.3; title: For -- 82 -- 2.10.4; title: If Then -- 83 -- 2.10.5; title: If Else -- 85 -- 2.11; title: Annulled Unconditional Branch -- 88 -- 3; title: Digital Logic and Binary Numbers -- 97 -- 3.1; title: Binary Hardware Devices -- 97 -- 3.2; title: Decimal and Binary Number Systems -- 99 -- 3.2.1; title: Octal and Hexadecimal Numbers -- 100 -- 3.2.2; title: Converting from Decimal to Binary -- 102 -- 3.2.3; title: Converting from Binary to Decimal -- 104 -- 3.3; title: ASCII Representation of Characters -- 105 -- 3.4; title: Bitwise Logical Operations -- 105 -- 3.4.1; title: Synthetic Instructions Using %g0 -- 109 -- 3.4.2; title: Flags -- 111 -- 4; title: Binary Arithmetic -- 115 -- 4.2; title: Binary Numbers and Addition -- 115 -- 4.3; title: Half and Full Adders -- 117 -- 4.4; title: Modulus Arithmetic -- 117 -- 4.5; title: Subtraction -- 119 -- 4.6; title: Two's Complement Number Branching Conditions -- 122 -- 4.6.1; title: Shifting -- 123 -- 4.7; title: Unsigned Arithmetic -- 124 -- 4.8; title: Unsigned Number Branching Conditions -- 124 -- 4.9; title: Condition Code Tests -- 125 -- 4.10; title: Multiplication -- 125 -- 4.10.1; title: SPARC mulscc Instruction -- 131 -- 4.11; title: Division -- 134 -- 4.12; title: Extended Precision Arithmetic -- 139 -- 4.12.1; title: Addition of Extended Precision Numbers -- 139 -- 4.12.2; title: Subtraction of Extended Precision Numbers -- 139 -- 4.12.3; title: Multiplication of Extended Precision Numbers -- 141 -- 5; title: Stack -- 151 -- 5.1; title: Memory -- 151 -- 5.2.1; title: Frame Pointer -- 154 -- 5.3; title: Addressing Stack Variables -- 155 -- 5.3.1; title: Load Instructions -- 156 -- 5.3.2; title: Store Instructions -- 157 -- 5.4; title: Defining Stack Variable Offsets -- 157 -- 5.6; title: One-Dimensional Arrays -- 167 -- 5.7; title: Improvements to the Code -- 173 -- 6; title: Data Structures -- 181 -- 6.2; title: Array Storage and Addressing -- 181 -- 6.3; title: Multidimensional Arrays -- 182 -- 6.3.1; title: Lower Bounds Different from Zero -- 183 -- 6.3.2; title: Array Bound Checking -- 185 -- 6.4; title: Address Arithmetic -- 187 -- 6.5; title: Structures -- 190 -- 6.6; title: Structures as Automatic Variables -- 193 -- 6.6.1; title: Nested Structures -- 194 -- 7; title: Subroutines -- 203 -- 7.2; title: Open Subroutines -- 204 -- 7.3; title: Register Saving -- 204 -- 7.4; title: Subroutine Linkage -- 208 -- 7.5; title: Arguments to Subroutines -- 209 -- 7.7; title: Return Values -- 217 -- 7.8; title: Subroutines with Many Arguments -- 220 -- 7.9; title: Leaf Subroutines -- 221 -- 7.10; title: Pointers as Arguments to Subroutines -- 224 -- 8; title: Machine Instructions -- 231 -- 8.2; title: Instruction Decode -- 231 -- 8.3; title: Format Three Instructions -- 232 -- 8.4; title: Format One Instruction: The call Instruction -- 237 -- 8.5; title: Format Two Instructions -- 237 -- 8.5.1; title: Branch Instructions -- 238 -- 8.5.2; title: Loading 32-Bit Constants -- 242 -- 9; title: External Data and Text -- 247 -- 9.2; title: External Variables -- 247 -- 9.3; title: Text Section -- 248 -- 9.4; title: Data Section -- 248 -- 9.4.1; title: ASCII Data -- 252 -- 9.5; title: Pointers -- 253 -- 9.6; title: .Bss Section -- 254 -- 9.7; title: Switch Statement -- 255 -- 9.8; title: Relocation and Linking with Other Code -- 257 -- 9.9; title: Makefiles -- 261 -- 9.10; title: C Command Line Arguments -- 262 -- 10; title: Input/Output -- 271 -- 10.2; title: Memory Mapped I/O -- 271 -- 10.3; title: Character Devices -- 272 -- 10.4; title: Programmed I/O -- 272 -- 10.5; title: Interrupt-Driven I/O -- 275 -- 10.6; title: Block Devices -- 277 -- 10.7; title: Directory Devices -- 277 -- 10.8; title: Input/Output Processors -- 278 -- 10.9; title: System I/O -- 278 -- 11; title: Floating-Pointg -- 283 -- 11.2; title: Fixed Binary Point Numbers -- 284 -- 11.3; title: Scientific Notation -- 285 -- 11.4; title: Floating-Point -- 289 -- 11.5; title: Floating-Point Processor -- 290 -- 11.6; title: A Floating-Point Program -- 293 -- 11.6.1; title: Debugging Single Presision Floating-Point Code -- 295 -- 11.6.2; title: An Improved Version of the Code -- 296 -- 11.7; title: Floating NaNs -- 299 -- 11.8; title: Subnormal Numbers -- 299 -- 11.9; title: Extended Precision Floating-Point -- 300 -- 11.10; title: Debugging Floating Double Programs -- 304 -- 11.11; title: Floating Quad Format -- 309 -- 11.12; title: Function Calls -- 310 -- 11.13; title: Tagged Arithmetic -- 312 -- 11.13.1; title: Lisp -- 313 -- 12; title: Traps and Exceptions -- 329 -- 12.2; title: Processor State Registers -- 330 -- 12.2.1; title: Processor State Register -- 331 -- 12.2.2; title: Window Invalid Mask Register -- 331 -- 12.2.3; title: Trap Base Register -- 332 -- 12.2.4; title: Floating-Point Processor State Register -- 332 -- 12.3; title: Traps -- 333 -- 12.4; title: Window Traps -- 337 -- 13; title: Memory Management -- 347 -- 13.2; title: Virtual Memory and Paging -- 348 -- 13.3; title: Page Descriptor Cache -- 355 -- 13.4; title: Cache Memory -- 356 -- 13.5; title: Context Switching -- 357 -- 14; title: Other Architectures -- 359 -- 14.2; title: PDP-11 -- 360 -- 14.3; title: VAX-11 -- 366 -- 14.4; title: MIPS Architecture -- 373 -- 15; title: Ultra Sparc -- 379 -- 15.2; title: 64-Bit Virtual Memory Addresses -- 379 -- 15.3; title: Superscalar Execution -- 382 -- 15.3.1; title: Branch Prediction -- 384 -- 15.3.2; title: Branch on Integer Register -- 385 -- 15.3.3; title: Multiple Floating-Point Condition Codes -- 386 -- 15.3.4; title: Move Register on Condition -- 387 -- 15.4; title: Instruction and Data Prefetching -- 391 -- 15.5; title: Nonfaulting Loads -- 391 -- 15.6; title: Changes to Supervisor Mode -- 393 -- A; title: Macro Definitions -- 395 -- B; title: Register Name Macro Definitions -- 399 -- C; title: Multiplication by Constants -- 401 -- C.2; title: m4 Built-in Macros -- 401 -- C.3; title: Conversion to Binary -- 403 -- C.4; title: Conversion to a Base 31 Number -- 405 -- C.5; title: Instruction Generation -- 406 -- D; title: User Mode Machine Instructions -- 409 -- D.1; title: Syntax -- 409 -- D.2; title: Arithmetic Instructions -- 410 -- D.3; title: Logical Instructions -- 418 -- D.4; title: Shift Instructions -- 424 -- D.5; title: Load Instructions -- 425 -- D.6; title: Store Instructions -- 427 -- D.7; title: Integer Branch Instructions -- 429 -- D.8; title: Trap Instructions -- 438 -- D.9; title: Control Instructions -- 447 -- D.10; title: Floating-Point Instructions -- 450 -- D.11; title: Floating-Point Branch Instructions -- 465 -- E; title: Synthetic Instructions and Pseudo-Ops -- 473 -- F; title: Instructions Sorted Alphabetically -- 479 -- G; title: Powers of 2 -- 483 -- H; title: Macro Language Processor m4-- 485.