Analysis of exception data in a staging heirarchy
By: by Donald P. Gaver, Peter A. W. Lewis, Gerald S. Shedler
Contributors: Lewis, Peter Adrian Walter; Shedler, Gerald S.; Naval Postgraduate School (U.S.)
Publisher: Naval Postgraduate School
Published: 1974
Place of publication: Monterey, California
Language: eng
Number of pages: 435
Subjects: Multiprogramming (Electronic computers); Queuing theory
Other titles: IBM Journal of Research and Development. v. 18, no. 5.
Description: This paper is concerned with the analysis of program address trace data in a demand paged computer system having a three level staging hierarchy.  Our primary objective is to explore the data both graphically and numerically, using methods that may be useful when other data traces become available.  A secondary objective has been to fit plausible point-process type models to the data.  It is believed that the present approach, combining data-analytic procedures with probability modeling, will prove useful in understanding program behavioro and htus aid in the rational design of complex computer systems.
Notes: Reprinted from IBM Journal of research and development, v. 18 no. 5, September 1974.

Title from cover.

"NPS-55Gv55Lw74071"--Cover.

"July 1974"--Cover.

"Prepared for: Chief of Naval Research, Arlington, Virginia 22217."

Includes bibliographical references (p. 435)

"Approved for public release; distribution is unlimited"--Cover.

Technical report; 1974.