Asynchronous design on FPGA.
Published: 2004
Language: eng
Number of pages: 101
Description: The objectives have been achieved by designing three commonly used components in digital systems: (1) a self-timed completion-sensing adder, (2) an asynchronous pipelining protocol and (3) an asynchronous FIFO.The primary motivations for my research are: (1) asynchronous systems offer attractive potential advantages over synchronous systems and (2) the FPGA technology is becoming a viable alternative to the ASIC technology. The main objectives are to examine the trade-offs between synchronous and asynchronous systems and identify the difficulties and limitations of asynchronous circuit design on current synchronously-oriented FPGA design tools and architectures.The designs suggest that asynchronous designs on FPGA have some attractive potential advantages but are limited to the synchronously-oriented architecture. In conclusion, both a new asynchronous FPGA architecture and a new design tool with capabilities to understand asynchronous circuits are required in order to fully exploit the advantages of asynchronous circuits.
Notes: Adviser:  Safwat Zaky.

Thesis (M.A.Sc.)--University of Toronto, 2004.

Electronic version licensed for access by U. of T. users.

Source: Masters Abstracts International, Volume: 43-03, page: 0937.

MICR copy on microfiche (2 microfiches).