ALUs, multipliers and dividers with completion signals suitable for inclusion in an asynchronous environment
By: by Aryesh Amar.
Published: 1994
Language: eng
Number of pages: 111
Subjects: Asynchronous circuits -- Design and construction.; Anolog multipliers.; Arithmetic logic units.
Notes: Computer-produced typeface.

Thesis (M.S.)--Washington State University, 1994.

Includes bibliographical references (leaves 86-89).

"School of Electrical Engineering and Computer Science."