Stresses in solder joints of electronic packages
By: by David Salinas, and Philip Y. Shin
Contributors: Shin, Philip Y.; Naval Postgraduate School (U.S.). Dept. of Mechanical Engineering
Publisher: Naval Postgraduate School; Available from National Technical Information Service
Published: 1991
Place of publication: Monterey, Calif; Springfield, Va
Language: eng
Number of pages: 21
Subjects: Circuit boards; Chips(Electronic); Soldered joints; Stress analysis; Ceramic materials
Other titles: NPS-ME-92-001.
Description: Electronic chip packages are comprised of several components with different material      properties and geometries. One of the most basic electronic packages is the tri-assembly      system consisting of a chip attached to a board by a solder connection. During the fabrication      of this simple unit, the soldering process subjects the device to a thermal field. Since the three      components of the device have different material properties, in particular their Young's      modulii, Poissons ratios, and thermal coefficients of expansion, the mismatch in these      properties result in thermoelastic stresses. In addition to the thermal field arising from      fabrication, thermal fields and hence thermoelastic stresses, result from the operation of the      device itself. An investigation of stresses was undertaken. Two types of solder joints, a leaded      device and an unleaded device, were compared for effectiveness. Procedures are shown for      the analyses of these two types of solder joints. The analyses showed that the thermoelastic      stresses for the stiff unleaded connection are significantly greater, by a factor of 20 for the      particular arrangement studied in this report, than the stresses in the more flexible leaded      connection.
Notes: Cover title.

"NPS-ME-92-001."

"December 1991."

AD A245 799.

Includes bibliographical references (p. 21).

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