Design of CMOS RF integrated circuits and systems
By: Kiat Seng Yeo, Manh Anh Do, Chirn Chye Boon
Contributors: Do, Manh Anh; Boon, Chirn Chye
Publisher: World Scientific
Published: 2010
Place of publication: Singapore
Language: eng
Number of pages: 341
ISBN-13: 9789814271554
Subjects: Complementary Metal oxide semiconductors; Radio frequency integrated circuits; Wireless communication systems
Description: "This book provides the most comprehensive and in-depth coverage of the latest circuit design developments in RF CMOS technology. It is a practical and cutting-edge guide, packed with proven circuit techniques and innovative design methodologies for solving challenging problems associated with RF integrated circuits and systems. This invaluable resource features a collection of the finest design practices that may soon drive the system-on-chip revolution. Using this book's state-of-the-art design techniques, one can apply existing technologies in novel ways and to create new circuit designs for the future."--BOOK JACKET.
Notes: Includes bibliographical references and index.
Table of contents: title: Chapter 1. RF CMOS Systems on Chips; title: 1.1. Modern RF Mobile Technologies; title: 1.2. The RF Transceiver System; title: 1.3. Modulation and Demodulation Techniques; title: 1.4. Multiple Access Techniques; title: 1.5. Receiver Sensitivity and Linearity; title: 1.6. On-chip Power Amplifier; title: 1.7. The Cellular Phone Concept; title: 1.8. The CMOS RF Technology; title: References; title: Chapter 2. RF CMOS Devices and Process Design Kits; title: 2.1. Introduction; title: 2.2. RF Transistors; title: 2.2.1. BSIM3v3 Model; title: 2.2.2. BSIM4 Model; title: 2.2.3. Figure of Merit; title: 2.2.3.1. fT definition and extraction; title: 2.2.3.2. fMAX definition and extraction; title: 2.2.4. RF Parasitics in MOSFETs; title: 2.2.5. Scalable RF CMOS Transistor Modeling; title: 2.2.5.1. RF MOSFET model; title: 2.2.5.2. Gate resistance modeling; title: 2.2.5.3. Source and drain resistance modeling; title: 2.2.5.4. Gate to substrate capacitance and resistance modeling; title: 2.2.5.5. Gate to source and gate to drain capacitance modeling; title: 2.2.5.6. Drain to source capacitance modeling; title: 2.2.5.7. Substrate resistance modeling; title: 2.3. On-chip Inductors; title: 2.3.1. Spiral Inductors on Silicon; title: 2.3.1.1. Figure of merits; title: 2.3.2. Advantages of Silicon-based Spiral Inductors; title: 2.3.3. Identifying Loss Mechanisms in Silicon-based Spiral Inductors; title: 2.3.3.1. Metallization resistive loss; title: 2.3.3.2. Substrate capacitive and resistive loss; title: 2.3.3.3. Substrate eddy current; title: 2.3.4. Q-Factor Enhancement Techniques; title: 2.3.4.1. Q-factor enhancement using processing technologies; title: 2.3.4.2. Q-factor enhancement using active inductors; title: 2.3.4.3. Q-factor enhancement using coupled spiral coils; title: 2.3.4.4. Q-factor enhancement using layout optimization; title: 2.3.4.5. Q-factor enhancement using inductor device model; title: 2.3.4.6. Figure of merits for differential spiral inductors; title: 2.4. Baluns/Transformers; title: 2.4.1. The Ideal Transformer; title: 2.4.2. Transformer Types; title: 2.4.3. Inductance, Capacitance, and Resistance; title: 2.4.4. Coupling Coefficient k, Turn Ratio n, and Quality Factor Q; title: 2.4.5. Patterned Ground Shield; title: 2.4.6. Designing the Transformer; title: 2.5. RF Interconnects; title: 2.5.1. Transmission Line Concept; title: 2.5.1.1. Transmission line constants; title: 2.5.1.2. Transmission line impedances; title: 2.5.1.3. Reflection and voltage standing wave ratio; title: 2.5.1.4. Frequency-dependent charge distribution; title: 2.5.1.5. Effects of dielectric on interconnects; title: 2.5.2. Existing Methodologies to Tackle Post Layout Parasitics; title: 2.5.3. Proposed Figure of Merit for RF Interconnects; title: 2.6. Varactors; title: 2.6.1. Functions of Varactors; title: 2.6.2. Varactor Design; title: 2.7. RF Capacitors; title: 2.7.1. Capacitance; title: 2.7.2. Geometry; title: 2.7.3. Quality Factor and Series Resistance; title: 2.7.4. Capacitance Modeling; title: 2.7.5. Impedances; title: 2.7.6. Design Considerations; title: 2.8. Process Design Kits; title: 2.8.1. Benefits; title: 2.8.2. Advanced Device Modeling and Front-end Design; title: 2.8.3. Back-end Design and Accelerated Layout; title: 2.8.4. Physical Verification and Silicon Analysis; title: 2.8.5. Future of Process Design Kits; title: 2.9. Summary; title: References; title: Chapter 3. RF CMOS Low Noise Amplifiers; title: 3.1. Basic Concepts of LNAs; title: 3.1.1. Operating Frequency; title: 3.1.2. Sensitivity; title: 3.1.3. Noise Figure and Voltage Gain; title: 3.1.4. 1 -dB Compression Point; title: 3.1.5. The 3rd Order Intercept Point; title: 3.1.6. S-Parameters; title: 3.2. Input Architecture of LNAs; title: 3.2.1. Common Source Stage with Resistive Termination; title: 3.2.2. Common Gate Stage; title: 3.2.3. Common Source Stage with Shunt Feedback; title: 3.2.4. Common Source Stage with Source Inductive Degeneration; title: 3.3. Input Matching Analysis; title: 3.4. Design of a Single-band LNA (LNA1); title: 3.4.1. Noise Figure Optimization; title: 3.4.2. Design Methodology; title: 3.4.3. Measurement Results; title: 3.5. Summary; title: References; title: Chapter 4. RF Mixers; title: 4.1. Introduction; title: 4.2. Common Configurations of Active Mixers; title: 4.3. Active Mixer with Current Booster; title: 4.4. Passive Mixers; title: 4.5. Port Isolation and DC Offset in Direct Conversion Mixers; title: 4.6. Image Reject Mixers for Low IF Architectures; title: References; title: Chapter 5. RF CMOS Oscillators; title: 5.1. Introduction; title: 5.1.1. Ring Oscillator; title: 5.1.2. LC Oscillator; title: 5.2. Various LC VCO Topologies; title: 5.2.1. Colpitts and HartleyLC VCOs; title: 5.2.2. Differential LC VCOs; title: 5.2.2.1. Complementary LC VCOs; title: 5.2.2.2. Tail current source of LC VCOs; title: 5.3. LC VCO Design Methodology; title: 5.3.1. Topology; title: 5.3.1.1. Operation theory; title: 5.3.1.2. Equivalent circuit of cross-coupled LC tank VCO; title: 5.3.2. Associated Noise Sources of Complementary LC Tank VCO; title: 5.3.2.1. Noise sources of the LC tank; title: 5.3.2.2. Upconversion of 1/f noise in the tail transistor; title: 5.3.3. Noise Sources in Active Devices; title: 5.3.3.1. High frequency noise; title: 5.3.3.2. Noise sources in cross-coupled transistors; title: 5.3.3.3. Optimization of channel length Lch; title: 5.3.4. Linear Time Variant (LTV) Phase Noise Analysis; title: 5.3.4.1. Definition of Impulse Sensitivity Function (ISF)-&Gamma;(&omega;0t); title: 5.3.4.2. Parameterized phase impulse response h&phi; (t, &tau;) using ISF; title: 5.3.4.3. Phase noise calculation; title: 5.3.4.4. Steps to achieve minimal phase noise; title: 5.3.5. A 2GHz Cross-Coupled LC Tank VCO; title: 5.3.5.1. 2GHz cross-coupled LC tank VCO; title: 5.3.5.2. Verifications and discussions; title: 5.3.5.3. Experimental results; title: 5.3.6. A 9.3  ̃10.4GHz Cross-Coupled Complementary Oscillator; title: 5.3.6.1. Phase noise estimation for 10GHzLC tank VCO; title: 5.3.6.2. Experimental results; title: 5.4. Summary; title: References; title: Chapter 6. RF CMOS Phase-Locked Loops; title: 6.1. Fundamental Principles of a Phase-Locked Loop (PLL); title: 6.2. Transient Characteristics - Tracking; title: 6.3. Loop Bandwidth - Second Order PLL; title: 6.4. Acquisition; title: 6.5. Phase Detector and Loop Filter; title: 6.5.1. Phase Detector; title: 6.5.1.1. Multiplier; title: 6.5.1.2. EXOR gate; title: 6.5.1.3. Flip-flop phase detector; title: 6.5.1.4. Phase frequency detector; title: 6.5.2. Loop Filter; title: 6.6. Charge Pump PLL Filter; title: 6.7. Noise Characteristics of PLL Building Blocks; title: 6.7.1. Phase Noise of VCO; title: 6.7.2. Phase Noise of Reference Input Signal; title: 6.7.3. Phase Noise of Frequency Divider; title: 6.7.4. Phase Noise of Loop Filter; title: 6.7.5. Optimum Loop Bandwidth; title: 6.8. Summary; title: References; title: Chapter 7. RF CMOS Prescalers; title: 7.1. Prescaler; title: 7.1.1. Dual-Modulus Prescaler; title: 7.1.2. Dual-Modulus Prescaler with Pulse Swallow Counter; title: 7.1.3. Integer-N Architecture through Dual-Modulus Prescaler with Pulse Swallow Counter; title: 7.2. DFFs for Prescaler; title: 7.2.1. MCML; title: 7.2.2. CMOS Dynamic Circuit; title: 7.3. Design and Optimization of CMOS Dynamic Circuit (CDC) Based Prescaler; title: 7.3.1. E-TSPC Based Divide-by-2 Unit; title: 7.3.2. E-TSPC Based Divide-by-2/3 Unit; title: 7.3.3. Design Example; title: 7.3.4. Simulation and Silicon Verifications; title: 7.4. Summary; title: References.