An adjustable Comparator for 2-bit/step SAR ADC Configuring with multiple samples per second in 40nm CMOS
Publisher: Association of Scientists, Developers and Faculties
Published: 2016
Place of publication: Chennai, India
Language: eng
ISBN-13: 9788192986654
Description: A low-power 2-bit/step operation technique is proposed which uses dynamic threshold configuring comparator instead of multiple digital-to-analog converters (DACs). Power and area overhead is minimized by successively activated comparators.  The comparator threshold is configured by simple Vcm biased current source, which keep the ADC free from power supply variations over 10%. To implement power efficient and high performance analog-to-digital converters the designers are urged to design an optimized dual tail comparator. In this paper, It is shown that in the proposed dual tail comparator both the power and delay time is significantly reduced.