Troubleshooting on microprocessor based systems
By: G.B. Williams.
Edition: 1st ed.
Series: The Pergamon materials engineering practice series
Publisher: Pergamon Press
Published: 1984
Place of publication: Oxford; New York
Language: eng
Number of pages: 213
Subjects: Microcomputers -- Testing.; Debugging in computer science.
Notes: Bibliography: p. 210.
Includes index.
Table of contents: label: 1
title: Introduction to Microprocessor Based Systems
pagenum: 1; label: 1.1
title: The Digital Computer
pagenum: 2; label: 1.2
title: Bus Structured Systems
pagenum: 3; label: 1.3
title: Memory Mapped Systems
pagenum: 6; label: 1.4
title: Tri-state Devices
pagenum: 7; label: 1.5
title: Address Decoding
pagenum: 9; label: 1.6
title: A Microcontroller
pagenum: 16; label: 1.7
title: Programming Levels
pagenum: 18; label: 2
title: System Testing Problems
pagenum: 24; label: 2.1
title: Hardware or Software?
pagenum: 25; label: 2.2
title: Time: Sequential, Bit-Parallel Data
pagenum: 25; label: 2.3
title: Bus Multiplexing
pagenum: 26; label: 2.4
title: The Device Testing Problem
pagenum: 26; label: 2.5
title: The System Kernel
pagenum: 28; label: 2.6
title: CPU Testing
pagenum: 30; label: 2.7
title: ROM Testing
pagenum: 30; label: 2.8
title: RAM Testing
pagenum: 33; label: 2.9
title: Input/Output Testing
pagenum: 36; label: 2.10
title: Some Common System Problems
pagenum: 37; label: 2.10.1
title: Power Supplies
pagenum: 37; label: 2.10.2
title: System Clocks
pagenum: 41; label: 2.10.3
title: Reset Circuits
pagenum: 42; label: 2.10.4
title: Interrupts
pagenum: 45; label: 2.10.5
title: Memory Devices
pagenum: 47; label: 2.10.6
title: Signal Degradation
pagenum: 48; label: 3
title: System Testing Philosophy
pagenum: 50; label: 3.1
title: Self-test Programs
pagenum: 52; label: 3.2
title: Is There Really a Fault?
pagenum: 53; label: 3.3
title: The Life-cycle of an Integrated Circuit
pagenum: 55; label: 3.4
title: Stress Testing
pagenum: 56; label: 3.4.1
title: Mechanical Stressing
pagenum: 57; label: 3.4.2
title: Thermal Stressing
pagenum: 57; label: 3.4.3
title: Electrical Stressing
pagenum: 58; label: 3.5
title: Isolation Techniques
pagenum: 58; label: 3.6
title: The Troubleshooting Tree
pagenum: 61; label: 4
title: The Use of Conventional Test Equipment
pagenum: 65; label: 4.1
title: Multimeters
pagenum: 65; label: 4.2
title: Frequency Counters
pagenum: 66; label: 4.3
title: The Oscilloscope
pagenum: 67; label: 4.4
title: The Limitations of Conventional Test Equipment
pagenum: 71; label: 5
title: Hand-held Tools
pagenum: 73; label: 5.1
title: Logic Probes
pagenum: 74; label: 5.1.1
title: Commercial Logic Probes
pagenum: 79; label: 5.1.2
title: Using a Logic Probe
pagenum: 80; label: 5.2
title: Logic Pulsers
pagenum: 82; label: 5.2.1
title: Using a Logic Pulser
pagenum: 83; label: 5.3
title: Stimulus-response Testing Using a Pulser and Probe
pagenum: 86; label: 5.4
title: The Current Tracer
pagenum: 87; label: 5.4.1
title: Using the Current Tracer
pagenum: 90; label: 5.4.2
title: Stimulus-response Testing Using the Logic Pulser and Current Tracer
pagenum: 90; label: 5.4.2.1
title: Wire-AND Nodes
pagenum: 91; label: 5.4.2.2
title: Gate-to-gate Faults
pagenum: 92; label: 5.4.2.3
title: Solder Bridges and Cable Problems
pagenum: 93; label: 5.4.2.4
title: Multiple Gate Inputs
pagenum: 93; label: 5.4.2.5
title: Power Supply Short Circuits
pagenum: 94; label: 5.5
title: Logic Comparators
pagenum: 95; label: 5.6
title: The Limitations of Hand-held Tools
pagenum: 96; label: 6
title: Logic Analysers
pagenum: 98; label: 6.1
title: Logic State Analysers
pagenum: 100; label: 6.2
title: Logic Timing Analysers
pagenum: 111; label: 6.3
title: Display Modes
pagenum: 114; label: 6.3.1
title: The MAP Mode
pagenum: 114; label: 6.3.2
title: State Flow — Binary and Grouped Binary
pagenum: 117; label: 6.3.3
title: State Flow — Hexadecimal Format
pagenum: 119; label: 6.3.4
title: State Flow — Disassembled Format
pagenum: 121; label: 6.3.5
title: Timing Displays
pagenum: 121; label: 6.3.6
title: Special Coding Formats
pagenum: 122; label: 6.4
title: Logic Analyser Features
pagenum: 122; label: 6.4.1
title: Counting Events
pagenum: 124; label: 6.4.2
title: Time Interval Measurements on a Logic State Analyser
pagenum: 125; label: 6.4.3
title: Trigger Ranges and Trigger Occurrence
pagenum: 127; label: 6.4.4
title: Pre- and Post-triggering
pagenum: 128; label: 6.4.5
title: Personality Modules
pagenum: 128; label: 6.4.6
title: Qualifiers on Logic Timing Analysers
pagenum: 129; label: 6.4.7
title: Accessories
pagenum: 129; label: 7
title: Signature Analysers
pagenum: 131; label: 7.1
title: The Nature of Digital Waveforms
pagenum: 132; label: 7.2
title: Transition Counting
pagenum: 133; label: 7.3
title: The Probability of Success Using the Transition Counting Technique
pagenum: 134; label: 7.4
title: Cyclic Redundancy Check Codes
pagenum: 138; label: 7.5
title: Signature Analysis
pagenum: 140; label: 7.6
title: The Probability of Success Using Signature Analysis
pagenum: 143; label: 7.6.1
title: Error Detection Using Signature Analysis
pagenum: 146; label: 7.7
title: A Simple Signature Analyser
pagenum: 149; label: 7.8
title: Free-run Testing Using a Signature Analyser
pagenum: 153; label: 7.9
title: ROM Testing During Free-run
pagenum: 157; label: 7.10
title: Signature Analysis Test Loops
pagenum: 158; label: 7.11
title: Retrofitting Signature Analysis
pagenum: 159; label: 7.12
title: Limitations of Signature Analysis
pagenum: 160; label: 7.13
title: Signature Analysis as a General Test Technique
pagenum: 161; label: 8
title: Emulation
pagenum: 163; label: 8.1
title: Development Systems
pagenum: 164; label: 8.1.1
title: The Editor
pagenum: 165; label: 8.1.2
title: The File Manager
pagenum: 167; label: 8.1.3
title: The Linker/Loader
pagenum: 167; label: 8.1.4
title: The I/O Device Handler
pagenum: 168; label: 8.1.5
title: Assemblers
pagenum: 169; label: 8.1.6
title: Compilers
pagenum: 171; label: 8.1.7
title: The Memory Manager
pagenum: 172; label: 8.1.8
title: The Debugger
pagenum: 173; label: 8.1.9
title: A Real-time Analyser
pagenum: 174; label: 8.1.10
title: An EPROM Programmer
pagenum: 174; label: 8.1.11
title: In-circuit Emulators
pagenum: 175; label: 8.2
title: System Testing Using a Development System
pagenum: 175; label: 8.3
title: Stand-alone Emulators
pagenum: 176; label: 9
title: Self-test and Diagnostic Software
pagenum: 179; label: 9.1
title: Self-test Routines
pagenum: 180; label: 9.1.1
title: ROM Testing
pagenum: 180; label: 9.1.2
title: RAM Testing
pagenum: 182; label: 9.2
title: Diagnostic Tests
pagenum: 185; label: 9.2.1
title: Simple I/O Testing
pagenum: 186; label: 9.2.2
title: Initiating Diagnostic Tests
pagenum: 188; label: 10
title: Testing Peripheral Related Functions
pagenum: 189; label: 10.1
title: An Example of Sub-system Functional Testing
pagenum: 190; label: 10.2
title: Testing Serial Data Communication Lines
pagenum: 192; label: 10.2.1
title: Serial Transmission Protocols
pagenum: 195; label: 10.2.2
title: Baud Rates
pagenum: 197; label: 10.2.3
title: An Asynchronous Communications Interface
pagenum: 198; label: 10.3
title: Monitoring the IEEE-488 Instrumentation Bus
pagenum: 202; label: 10.3.1
title: The GPIB Structure
pagenum: 203; label: 10.3.2
title: An Example of a Bus Transfer on the GPIB
pagenum: 207; label: 10.3.3
title: Analysing the GPIB Signals
pagenum: 208; title: References
pagenum: 210; title: Index
pagenum: 211