Transistor sizing for timing optimization of combinational digital CMOS circuits
By: presented by Lucas Sebastian Heusler.
Publisher: Hartung-Gorre Verlag
Published: 1990
Place of publication: [Konstanz, Switzerland
Language: eng
Number of pages: 102
Subjects: Metal oxide semiconductors, Complimentary -- Design and construction.; Transistor-transistor logic circuits -- Design and construction.
Notes: "Accepted on the recommendation of W. Fichtner, W. Guggenbühl."

Abstract in English and German.

Thesis (Doctoral)--Swiss Federal Institute of Technology, Zurich, 1990.

Includes bibliographical references.