Low-power asynchronous Viterbi decoder for wireless applications.
Published: 2004
Language: eng
Number of pages: 56
Description: Power dissipation is a critical parameter in digital design for the implementation of high performance portable, battery operated systems, such as wireless communications systems. Clocked or synchronous digital designs consume a significant amount of power associated with coordinating the operation of millions of transistors at GHz clock rates. Besides, the operating speed of such systems is limited by the slowest logic functional block. By contrast, asynchronous designs are active only when doing useful work, enabling considerable savings in power and operating at the average speed of all components.To illustrate the advantages of asynchronous logic design, a 64-state, 112-rate fully asynchronous Viterbi decoder, suitable for future generation wireless applications, was designed and implemented in a 0.18 mum CMOS technology, using a simple asynchronous design methodology that resembles synchronous design styles. The design was fully characterized and compared to a synchronously designed counterpart as well as to the state of the art Viterbi decoders. The implemented asynchronous Viterbi had a core area of 1.4 x 1.4 mm 2 and operated up to 213 Mbps while consuming 85 mW. This represents a 55% power saving when compared to previously reported state of the art designs.
Notes: Adviser:  C. A. T. Salama.

Thesis (M.A.Sc.)--University of Toronto, 2004.

Electronic version licensed for access by U. of T. users.

Source: Masters Abstracts International, Volume: 42-06, page: 2286.

MICR copy on microfiche (1 microfiche).