Verification by error modeling
Subtitle: using testing techniques in hardware verification
By: written by Katarzyna Radecka, Zeljko Zilic.
Contributors: Zilic, Zeljko.
Series: Frontiers in electronic testing -- 25
Publisher: Kluwer Academic Publishers
Published: 2003
Place of publication: Boston
Language: eng
Number of pages: 216
Subjects: Integrated circuits -- Very large scale integration -- Computer-aided design.; Integrated circuits -- Verification.; Error analysis (Mathematics)
Notes: Includes bibliographical references and index.