Designing fast Golay encoder/decoder in Xilinx XACT with Mentor Graphics CAD interface
By: Mehmet Sari
Publisher: Naval Postgraduate School; Available from National Technical Information Service
Published: 1997
Place of publication: Monterey, Calif; Springfield, Va
Language: eng
Number of pages: 94
Description: The programmable logic array is one of the most fascinating and fast developing areas of technology. Field programmable gate arrays are becoming prevalent in design as the density of the gate arrays goes up. In this thesis study, a fast encoding/decoding algorithm, Extended Golay Coding, is implemented in Xilinx XC4000 family programmable gate array (FPGA) architecture. The encoder/decoder is designed using the Xilinx XACT tool with the Mentor Graphics schematic capture Design Architect (DA) and Quicksimll simulation interfaces. With the static RAM bits onboard the new Xilinx FPGAs, the architecture is more powerful, and it is relatively easy to upgrade the old design based on the needs of the users. In this thesis, fast encoder/decoder is implemented with transmission word redundancy and interleaving. This is based on the data link layer description of the Misted 181-144A. The FPGA static RAM bits are used for the encode and decode ROM of the algorithm that makes the coder faster. Modular approach and design hierarchy made design tasks easier and upgradable in this study. The timing simulations of some design modules will be presented. Due to the complexity of the circuits, it is found that the design has to be migrated to a higher density chip than X04003 used in the simulations.
Notes: Thesis advisor(s): Chin-Hwa Lee.

"March 1997."

Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, March 1997.

Includes bibliographical references (p. 91).

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