Proceedings
Subtitle: International Workshop on Memory Technology, Design, and Testing
By: edited by F. Lombardi, R. Rajsuman, and T. Wik ; sponsored by IEEE Computer Society, IEEE Computer Society Technical Committee on Test Technology, IEEE Computer Society Technical Committee on VLSI ; in cooperation with IEEE Solid State Circuits Council.
Contributors: Lombardi, Fabrizio, 1955-; Rajsuman, Rochit.; Wik, T.; IEEE Computer Society. Test Technology Technical Committee.; IEEE Computer Society. Technical Committee on VLSI.
Publisher: IEEE Computer Society Press
Published: 1997
Place of publication: Los Alamitos, Calif
Language: eng
Number of pages: 103
Subjects: Semiconductor storage devices -- Testing -- Congresses.; Random access memory -- Congresses.
Other titles: Records of the IEEE International Workshop on Memory Technology, Design and Testing; Memory Technology, Design and Testing; MTDT'97
Notes: Includes bibliographical references and index.
"August 11-12, 1997, San Jose, California"--Cover.
"IEEE Order Plan Catalog Number 95TB100159"--T.p. verso.
"IEEE Computer Society Order Number PR08099"--T.p. verso.
Table of contents: value: Matching memory to the power of personal computers / R. Foss; value: A low-cost, high performance three-dimensional memory module technology / A. Glaser ... [et al.]; value: High speed circuit techniques in a 150MHz 64M SDRAM / V. Lines ... [et al.]; value: An analysis of (linked) addressed decoder faults / A. van de Goor, G. Gaydadjiev; value: SRAM yield estimation in the early stage of the design cycle / V. Kim, T. Chen; value: False write through and un-restored write electrical level fault models for SRAMs / R. Adams, E. Cooley; value: A defect-tolerant DRAM employing a hierarchical redundancy scheme, built-in self-test and self-reconfiguration / D. Niggemeyer, J. Otterstedt, M. Redeker; value: Formal verification of memory arrays using symbolic trajectory evaluation / M. Pandey, R. Bryant; value: A product development flow with metrics for memory designs / S. Hegde, I. Pal, K. Rao; value: A low-power high storage capacity structure for GaAs MESFET ROM / R. Kanan ... [et al.]; value: Use of selective precharge for low-power on the match lines of content-addressable memories / C. Zukowski, S. Wang; value: An open notation for memory tests / A. Offerman, A. van de Goor; value: Testing memory modules in SRAM-based configurable FPGAs / W. Huang ... [et al.]; value: Memory array testing through a scannable configuration / S. Yano, N. Ishiura; value: A high-speed parallel sensing scheme for multi-level non-volatile memories / C. Calligaro ... [et al.].