Designing asynchronous circuits using NULL convention logic (NCL)
By: Scott C. Smith and Jia Di
Contributors: Di, Jia
Series: Synthesis lectures on digital circuits and systems -- # 23
Publisher: Morgan & Claypool Publishers
Published: 2009
Place of publication: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA)
Language: eng
Format: [electronic resource] /
ISBN-13: 9781598299823; 9781598299816
Subjects: Logic design; Symbolic and mathematical Logic; Sequential circuits; Combinational circuits; Asynchronous circuits; Design and construction
Other titles: Synthesis digital library of engineering and computer science.
Description: Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power.
Notes: Part of: Synthesis digital library of engineering and computer science.

Title from PDF t.p. (viewed on August 9, 2009).

Series from website.

Includes bibliographical references.

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Also available in print.

Mode of access: World Wide Web.

System requirements: Adobe Acrobat reader.
Table of contents: title: Introduction to asynchronous logic; title: Overview of NULL convention logic (NCL); title: NCL system framework and fundamental components; title: Transistor-level NCL gate design; title: Combinational NCL circuit design; title: Input-completeness and observability; title: Dual-rail NCL design; title: Quad-rail NCL design; title: Sequential NCL circuit design; title: NCL implementation of Mealy and Moore machines; title: NCL implementation of algorithmic state machines; title: NCL throughput optimization; title: Pipelining; title: Embedded registration; title: Early completion; title: NULL cycle reduction; title: Low-power NCL design; title: Wavefront steering; title: Multi-threshold CMOS (MTCMOS) for NCL (MTNCL); title: MTCMOS for synchronous circuits; title: Implementing MTCMOS in NCL circuits; title: Comprehensive NCL design example.