Verification issues of virtual components in system-on-a-chip (SOC) designs
By: Manfred Stadler
Series: Series in microelectronics -- v. 104
Publisher: Hartung-Gorre
Published: 2000
Place of publication: Konstanz
Language: eng
Number of pages: 180
Subjects: Systems on a chip; Testing; Integrated circuits; Verification; Modularity (Engineering)
Notes: Originally presented as the author's thesis (Swiss Federal Institute of Technology), Diss. ETH No. 13814.

Includes bibliographical references (p. 171-178).

Abstract in English and in German.