Multiple-valued programmable logic array minimization by concurrent multiple and mixed simulated annealing
Contributors: Butler, Jon T.
Publisher: Naval Postgraduate School; Available from the National Technical Information Service
Published: 1992
Place of publication: Monterey, Calif; Springfield, Va
Language: eng
Number of pages: 53
Notes: Thesis advisor, Jon T. Butler.

AD-A260379.

Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, Dec. 1992.

Includes bibliographical references.