IEEE standard for SystemVerilog--unified hardware design, specification, and verification language
By: sponsor, Design Automation Standards Committee of the IEEE Computer Society and the IEEE Standards Association Corporate Advisory Group
Contributors: IEEE Standards Association. Corporate Advisory Group; Institute of Electrical and Electronics Engineers; IEEE-SA Standards Board
Edition: 2nd printing: 1 Feb. 2010. Correction to the Table of Contents.
Series: IEEE Std
Publisher: Institute of Electrical and Electronics Engineers
Published: 2010
Place of publication: New York
Language: eng
Format: [electronic resource] /
Number of pages: 1247
ISBN-13: 9780738161297
Subjects: Computer hardware description languages; Verilog (Computer hardware description language); Standards
Other titles: IEEE standard for System Verilog--unified hardware design, specification, and verification language; IEEE Std 1800-2009 (Revision of IEEE Std1800-2005)
Description: Abstract: This standard represents a merger of two previous standards: IEEE Std 1364-2005 Verilog hardware description language (HDL) and IEEE Std 1800-2005 SystemVerilog unified hardware design, specification, and verification language. The 2005 SystemVerilog standard defines extensions to the 2005 Verilog standard. These two standards were designed to be used as one language. Merging the base Verilog language and the SystemVerilog extensions into a single standard provides users with all information regarding syntax and semantics in a single document. Keywords: assertions, design automation, design verification, hardware description language, HDL, HDVL, PLI, programming language interface, SystemVerilog, Verilog, VPI.
Notes: "IEEE Std 1800-2009 (Revision of IEEE Std1800-2005)."

"Approved 11 November 2009, IEEE-SA Standards Board."

"Published 11 December 2009 ; STD96001"--Page ii.

Title from title page (viewed Mar. 16, 2010).

Includes bibliographical references (page 1247).