Mixed-signal VLSI adiabatic array computing.
Published: 2006
Language: eng
Number of pages: 71
ISBN-13: 9780494211328
Description: The processors employ a resonantly-adiabatic mixed-signal VLSI computational array, with the oscillator tank comprised of the on-chip load capacitance and an off-chip inductor. The massively parallel nature of the architecture allows to reduce adiabatic resistive losses by lowering clock frequency while maintaining high computational throughput. Energy losses are further minimized by keeping the on-chip load capacitance near its mean value for any input data, maintaining the resonance at its nominal frequency.The 256x512 resonantly-adiabatic computational array is validated in template-based face detection, and spectral analysis of neural recordings.Many real time signal processing algorithms require a large number of multiply-and-accumulate (MAC) operations per second to perform computationally expensive matrix transforms in real time. Implantable and wearable implementations impose an additional constraint of a small power budget. This thesis presents two adiabatic parallel processor designs satisfying both of these requirements.
Notes: Source: Masters Abstracts International, Volume: 45-03, page: 1602.

Advisor: Roman Genov.

Thesis (M.A.Sc.)--University of Toronto, 2006.

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