An FPGA-based hardware development system with multi-gigabyte memory capacity and high bandwidth.
Published: 2005
Language: eng
Number of pages: 156
Description: FPGA-based hardware development systems are extremely useful for exploring exciting applications in vision, graphics, and many other computationally intensive problems. Experience with previous systems has shown that memory capacity, inter-FPGA bandwidth, host-to-FPGA bandwidth, and memory bandwidth are all critical to the successful implementation of high performance systems. This thesis presents the design, and implementation, of a new FPGA-based development system that was created with the goal of providing as much performance in these four areas as feasible. The design was built with 8GB of memory and its bandwidth performance was measured. The system has 17.6GB/s total aggregate memory bandwidth, and 154MB/s (read) and 266MB/s (write) host-to-FPGA bandwidth. The result is a working development system that is capable of implementing the applications of the future.
Notes: Thesis (M.A.Sc.)--University of Toronto, 2005.

Electronic version licensed for access by U. of T. users.

Source: Masters Abstracts International, Volume: 44-01, page: 0466.

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