Delay Insensitive Circuits -- Structures, Semantics, and Strageties
Edition: ebook version
Publisher: Plumstead Publishing House
Published: 2019
Place of publication: London, UK
Format: ebook
Number of pages: 652
ISBN-13: 9781916168107
Copyright date: 2019
Table of contents: pagenum: 15
title: Background and Motivation
label: Part 1; pagenum: 17
title: Why to Study Delay Insensitive circuits
label: Chapter 1; pagenum: 25
title: Why Delay Insensitive Design is Challenging
label: Chapter 2; pagenum: 41
title: The Lay of the Land
label: Chapter 3; pagenum: 67
title: Success
label: Chapter 4; pagenum: 85
title: Formal Models
label: Part 2; pagenum: 87
title: Petri Net Plumbing
label: Chapter 5; pagenum: 121
title: Reachability Graph Wrangling
label: Chapter 6; pagenum: 157
title: Transducer Tuning
label: Chapter 7; pagenum: 195
title: Block Building
label: Chapter 8; pagenum: 235
title: Module Families
label: Part 3; pagenum: 237
title: As Primitive as Can Be
label: Chapter 9; pagenum: 271
title: Decisions, Decisions
label: Chapter 10; pagenum: 315
title: Thin on the Ground
label: Chapter 11; pagenum: 361
title: All About Arbiters
label: Chapter 12; pagenum: 411
title: Putting the Word Out
label: Chapter 13; pagenum: 449
title: Working on the Railroad
label: Chapter 14; pagenum: 489
title: Synthesis
label: Part 4; pagenum: 491
title: State Based Synthesis
label: Chapter 15; pagenum: 533
title: Direct Mapping Synthesis
label: Chapter 16; pagenum: 573
title: Appendices
label: Part 5; pagenum: 575
title: Supplementary Remarks on Quasi-Delay Insensitivity
label: Appendix A; pagenum: 579
title: Complete Partial Orderings and Fixed Points
label: Appendix B; pagenum: 587
title: Decision Wait Metrics
label: Appendix C; pagenum: 603
title: Latency Arithmetic
label: Appendix D; pagenum: 609
title: Arbiter Metrics
label: Appendix E; label: Appendix F
title: Dual Rail Buffer Cell Theory of Operation