Single-event analysis of LT GaAs MESFET integrated circuits
Publisher: Naval Postgraduate School; Available from National Technical Information Service
Published: 1997
Place of publication: Monterey, Calif; Springfield, Va
Language: eng
Number of pages: 45
Description: There is a growing need for the use of electronics in radiation environments such as space. Gallium arsenide (GaAs) semiconductor technology is highly desirable for these applications because it consumes less power at higher speeds than silicon (Si) and shows superior radiation hardness over silicon technologies except for Single-Event-Upset (SEU). This thesis examines GaAs MESFETs fabricated in the Vitesse H-GaAsIII(R) process utilized in Direct Coupled FET Logic (DCFL) inverters. These simulations are targeted at determining the vulnerability of these devices to SEU. MESFETs fabricated on low-temperature grown GaAs (LT GaAs) epitaxial layers are investigated in addition to the conventional MESFET process using only bulk GaAs. Two- dimensional computer simulations are performed to determine the most effective method to simulate SEU charge collection mechanisms, and how effective the LT gaAs buffer layer is at reducing SEU vulnerability. This thesis is part of a larger project that is attempting to develop a new wafer design that can be inserted into the current Vitesse fabrication process to produce radiation hardened circuits. Computer simulations are performed using MIXEDMODE(R), which is a SPICE simulator for the ATLAS(R) device simulation software created by SILVACO International Inc.(R).
Notes: Thesis advisor, Todd R. Weatherford.

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, Sept. 1997.

Includes bibliographical references (p. 43-44).

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