VLSI design of a sixteen bit pipelined multiplier using three micron NMOS technology
Published: 1985
Language: eng
Number of pages: 94
Subjects: Electrical engineering
Notes: Available from National Technical Information Service, Springfield, Va.

ADA159433.

Thesis (M.S. in E.E.) Naval Postgraduate School, 1985.

Includes bibliographical references.

c.1 - 215252, c.2 - 215253