An 8-bit 2-GSample/s folding-interpolating analog-to-digital converter for LMDS applications.
Published: 2004
Language: eng
Number of pages: 102
Description: This thesis deals with the design and implementation of a high speed high resolution analog-to-digital converter (ADC) which is an essential component in a direct IF sampling receiver for the base station of LMDS wireless communication systems. The ADC features an 8-bit resolution, a 2-GSample/s sampling rate and is implemented in a 0.5 mum BiCMOS SiGe process with a unity gain cut off frequency of 47 GHz. A folding-interpolating architecture is used in the converter to provide the GHz sampling rate, wide bandwidth and high resolution as well as reduce the power dissipation and chip area of the circuit.The 8-bit, 2-GSample/s A/D converter consists of a track-and-hold amplifier, a reference ladder, four folding amplifiers, a comparator array, a digital encoder including an XOR array and a 31-to-5 ROM and a coarse quantizer. The chip area is 3.5 x 3.5 mm2 including pads and buffer circuits. The ADC exhibits a maximum signal-to-noise and distortion ratio (SNDR) of 47 dB corresponds to an effective number of bits (SNOB) of 7.45 bits and an effective resolution bandwidth (ERBW) of 700 MHz. The circuit demonstrates a maximum differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.5 and 1 LSB, respectively. The chip consumes 3.5 W from a single -3.3 V power supply. The ADC exceeds the LMDS architecture specifications and is the highest performance GSample/s ADC reported to date.Local multi-point distribution system (LMDS) is a terrestrial cellular broadband communication system operating in the 28 GHz band. LMDS provides two-way wireless transmission for data, video and voice and allows for interactive services.
Notes: Thesis (Ph.D.)--University of Toronto, 2004.

Electronic version licensed for access by U. of T. users.

Source: Dissertation Abstracts International, Volume: 65-05, Section: B, page: 2561.