Implementation of an affine-invariant feature detector in field-programmable gate arrays.
Published: 2006
Language: eng
Number of pages: 101
ISBN-13: 9780494211199
Description: Feature detectors are algorithms that can locate and describe points or regions of 'interest'---or features---in an image. As the complexity of the feature detection algorithm increases, so does the amount of time and computer resources required to perform it. For this reason, feature detectors are increasingly being ported to hardware circuits such as field-programmable gate arrays (FPGAs), where the inherent parallelism of these algorithms can be exploited to provide significant increase in speed.This work describes an FPGA-based implementation of the Harris-Affine feature detector introduced by Mikolajczyk and Schmid [36, 37]. The system is implemented on the Tra,nsmogrifier-4, a prototyping platform developed at the University of Toronto that includes four Altera Stratix S80 FPGAs and NTSC/VGA video interfaces. The system achieves a speed of 90--9000 times the speed of an equivalent software implementation, allowing it to process standard video (640 x 480 pixels) at 30 frames per second.
Notes: Source: Masters Abstracts International, Volume: 45-03, page: 1589.

Advisor: W. James MacLean.

Thesis (M.A.Sc.)--University of Toronto, 2006.

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