Highly Parallel Silicon Photonic Links with Integrated Kerr Frequency Combs
By: Anthony Rizzo
Publisher: [publisher not identified]
Published: 2022
Place of publication: [New York, N.Y.?]
Language: eng
Description: The rapid growth of data-intensive workloads such as deep learning and artificial intelligence has placed significant strain on the interconnects of high performance computing systems, presenting a looming bottleneck of significant societal concern. Furthermore, with the impending end of Moore's Law, continued reliance on transistor density scaling in compute nodes to compensate for this bottleneck will experience an abrupt halt in the coming decade. Optical interconnects provide an appealing path to mitigating this communication bottleneck through leveraging the favorable physical properties of light to increase bandwidth while simultaneously reducing energy consumption with distance-agnostic performance, in stark contrast to electrical signaling. In particular, silicon photonics presents an ideal platform for optical interconnects for a variety of economic, fundamental scientific, and engineering reasons; namely, (i) the chips are fabricated using the same mature complementary metal-oxide-semiconductor (CMOS) infrastructure used for microelectronic chips; (ii) the high index contrast between silicon and silicon dioxide permits micron-scale devices at telecommunication wavelengths; and (iii) decades of engineering effort has resulted in state-of-the-art devices comparable to discrete components in other material platforms including low-loss (< 0.5 dB/cm) waveguides, high-speed (> 100 Gb/s) modulators and photodetectors, and low-loss (< 1 dB) fiber-to-chip interfaces.

Through leveraging these favorable properties of the platform, silicon photonic chips can be directly co-packaged with CMOS electronics to yield unprecedented interconnect bandwidth at length scales ranging from millimeters to kilometers while simultaneously achieving substantial reduction in energy consumption relative to currently deployed solutions. The work in this thesis aims to address the fundamental scalability of silicon photonic interconnects to orders-of-magnitude beyond the current state-of-the-art, enabling extreme channel counts in the frequency domain through leveraging advances in chip-scale Kerr frequency combs. While the current co-packaged optics roadmap includes silicon photonics as an enabling technology to ~ 5 pJ/bit terabit-scale interconnects, this work examines the foundational challenges which must be overcome to realize forward-looking sub-pJ/bit petabit-scale optical I/O. First, an overview of the system-level challenges associated with such links is presented, motivating the following chapters focused on device innovations that address these challenges.

Leveraging these advances, a novel link architecture capable of scaling to hundreds of wavelength channels is proposed and experimentally demonstrated, providing an appealing path to future petabit/s photonic interconnects with sub-pJ/bit energy consumption. Such photonic interconnects with ultra-high bandwidth, ultra-low energy consumption, and low latency have the potential to revolutionize future data center and high performance computing systems through removing the strong constraint of data locality, permitting drastically new architectures through resource disaggregation. The advances demonstrated in this thesis provide a clear direction towards realizing future green hyper-scale data centers and high performance computers with environmentally-conscious scaling, providing an energy-efficient and massively scalable platform capable of keeping pace with ever-growing bandwidth demands through the next quarter-century and beyond.
Notes: Department: Electrical Engineering.

Thesis advisor: Keren Bergman.

Thesis (Ph.D.)--Columbia University, 2022.