Low-power hardware implementation of sound localization and speech separation.
Published: 2005
Language: eng
Number of pages: 100
Description: For the sound localization sub-system, low power consumption is achieved through a power analysis of an earlier design. This analysis shows that almost 75% (21.65 mW) of power is spent by the repetitive evaluation of cos(o) during the sound localization search. We have reduced this power consumption by quantizing the cosine function to seven levels; a power savings of 98.75% is achieved with insignificant change in localization error.This thesis presents a low-power (3.45 mW) hardware implementation of a sound localization and speech separation system. Sound localization is the process of estimating the location of a sound source using information gathered by two or more microphones. Speech separation is the process of extracting a speech signal of interest from a noisy recording.For the speech separation sub-system, low power consumption is achieved by sharing common processing blocks with the proposed sound localization sub-system. Moreover, by taking advantage of the leniency in the chosen speech separation algorithm (time-frequency masking) significant power savings are achieved through the use of a relatively coarse approximation of this algorithm. The proposed speech separation architecture performs similarly to the ideal (algorithmic floating point) implementation, in both noise reduction and speech recognition experiments.
Notes: Source: Masters Abstracts International, Volume: 44-01, page: 0468.

Thesis (M.A.Sc.)--University of Toronto, 2005.

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