Implementation of a Design for Testability strategy using the Genesil silicon compiler
By: John Carl Davidson
Contributors: Naval Postgraduate School (U.S.)
Publisher: Naval Postgraduate School
Published: 1989
Place of publication: Monterey, California
Language: eng
Number of pages: 115
Description: Design for Testability (DFT) is receiving major emphasis in the very large scale integration design field due to increasing circuit complexity. The utility of the silicon compiler and its value to a system designer without extensive VLSI design experience is discussed. Two major techniques for DFT, Scanpath Design and Built-in Test Design, are implemented using the Genesil silicon compiler. The basic building block, the shiftable test latch, is described in random logic block form and parallel datapath form. Linear feedback shift registers used as random vector generators and signature analyzers are used in the Built-in Test design. An Automatic Test Generation program is used to provide a measure of fault coverage for the two DFT techniques. The appendix is a brief tutorial illustrating the use of the Genesil system's shiftable test latch in its different configurations.
Notes: Thesis advisor: Loomis, Jr., Herschel H.

"March 1989."

Thesis (M.S. in Electrical Engineering) : Naval Postgraduate School, March 1989.

Includes bibliographic references.

Approved for public release, distribution unlimited.