A high-speed inter-process communication architecture for FPGA-based hardware acceleration of molecular dynamics.
Published: 2005
Language: eng
Number of pages: 91
Description: Molecular dynamics is a computationally intensive technique used in biomolecular simulations. We are building a hardware accelerator using a multiprocessor approach based on FPGAs. One key feature being leveraged is the availability of multi-gigabit serial transceiver technology (SERDES) available on the latest FPGAs. Computations can be implemented by a dedicated hardware element or a processor running software. Communication is implemented with a standard hardware interface abstraction. The actual communication is done via asynchronous FIFOs, if the communication is on-chip, or via Ethernet and SERDES, if the communication is between chips. The use of Ethernet is significantly slower than the SERDES, but allows for prototyping of the architecture using off-the-shelf development systems. A reliable, high-speed inter-FPGA communication mechanism using the SERDES channels has been developed. It allows for the multiplexing of multiple channels between chips. Bi-directional data-throughput of 1.918Gbps is achieved on a 2.5Gbps link and compared against existing communication methods.
Notes: Source: Masters Abstracts International, Volume: 44-02, page: 0987.

Thesis (M.A.Sc.)--University of Toronto, 2005.

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