Minimization of threshold voltage variations and their impact in circuits and FPGAs.
Published: 2005
Language: eng
Number of pages: 57
Description: Threshold voltage variations DeltaVth, resulting from underlying process variations, cause fluctuations in circuit delay that affect the chip timing yield. This thesis tackles Delta Vth in two ways: first by minimizing the timing sensitivity to DeltaVth in generic circuits and second by minimizing DeltaVth variations using adaptive-body biasing in FPGAs. We first study design techniques and optimization strategies that minimize the effects of threshold voltage variations on circuit delay variability. Specifically, we compare different static circuits and dynamic circuits and evaluate their limitations and benefits in terms of delay variability, performance penalty and area overhead. Based on our findings, we also introduce circuit design guidelines and techniques that help mitigate the effects of threshold voltage variations. By reducing delay variability on a per-gate basis, we show how one can build threshold voltage variations-aware gate libraries for use in deep submicron design.We then direct our efforts towards Field Programmable Gate Arrays (FPGAs) by proposing a novel architecture that cancels DeltaVth and minimizes leakage. FPGAs are attractive since they provide regular structures that are inherently prone to calibration and customization through configuration bits (SRAM, flash or antifuse). We take advantage of these features by providing additional configuration bits to a standard FPGA architecture that will adaptively body-bias each of these regular structures.
Notes: Source: Masters Abstracts International, Volume: 44-02, page: 0999.

Thesis (M.A.Sc.)--University of Toronto, 2005.

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