An engineering methodology for implementing and testing VLSI circuits
By: by Walter F. Corliss, II
Contributors: Naval Postgraduate School (U.S.)
Publisher: Naval Postgraduate School
Published: 1989
Place of publication: Monterey, California
Language: eng
Number of pages: 110
Description: The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined within this thesis. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix. (rh)
Notes: Thesis advisor: Loomis, Jr., Hershel H.

"March 1989."

Thesis (M.S. in Electrical Engineering) : Naval Postgraduate School, March 1989.

Includes bibliographical references.

Approved for public release, distribution unlimited.