Electromigration Modeling at Circuit Layout Level
By: by Cher Ming Tan, Feifei He
Contributors: He, Feifei; SpringerLink (Online service)
Series: SpringerBriefs in Applied Sciences and Technology
Publisher: Springer Singapore; Imprint: Springer
Published: 2013
Place of publication: Singapore
Language: eng
Format: [electronic resource] /
Number of pages: 103
ISBN-13: 9789814451215
Subjects: Engineering; Quality Control, Reliability, Safety and Risk; Electronic Circuits and Devices; System safety; Atomic, Molecular, Optical and Plasma Physics
Description: Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels.  Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is presented at circuit-layout level.
Table of contents: title: Introduction; title: 3D Circuit Model Construction and Simulation; title: Comparison of EM Performance in Circuit Structure and Test Structure; title: Interconnect EM Reliability Modeling at Circuit Layout Level; title: Conclusion.