High speed VLSI interconnections
Subtitle: modeling, analysis, and simulation
By: Ashok K. Goel.
Series: Wiley series in microwave and optical engineering
Publisher: Wiley-Interscience
Published: 1994
Place of publication: New York
Language: eng
Number of pages: 622
Subjects: Very high speed integrated circuits -- Mathematical models.; Very high speed integrated circuits -- Defects -- Mathematical models.; Integrated circuits -- Very large scale integration -- Computer simulation.; Semiconductors -- Junctions.
Description: High-Speed VLSI Interconnections is the first and only book of its kind. It focuses on a variety of numerical and computer techniques used for the modeling, analysis, and simulation of phenomena that have become major factors in the evolution of very high speed integrated circuit (VHSIC) technology.

Separate chapters are devoted to: parasitic effects such as capacitances and inductances, crosstalk, propagation delays, and electro-migration-induced failure, all of which are associated with VLSI interconnections. The final chapter discusses three interconnection technologies that may shape the future of integrated circuits.

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Each chapter is self-contained and can be read independently but also functions as part of a coherent overall presentation. Several techniques are provided for the analysis of each interconnection characteristic, and numerous illustrations provide the results of computer simulations. Challenging exercises at the end of each chapter are designed to help students gain further insight into the material presented.

End-of-chapter appendices contain source codes of several computer programs for simulating VLSI interconnections.

An excellent graduate-level text, High-Speed VLSI Interconnections offers a clear and accessible presentation of information that is not otherwise available in book form. As a professional reference, it is an indispensable source for researchers and engineers who seek a fuller understanding of this complex subject. It will also be of immense help to chip designers in developing VLSI interconnections with reduced parasitics, crosstalk, delay, and failure.
Notes: Includes bibliographical references (p. 595-616) and index.