A technique for evaluating the application of the pin-level stuck-at fault model to VLSI circuits
By: Daniel L. Palumbo and George B. Finelli.
Contributors: Finelli, George B.; United States. National Aeronautics and Space Administration. Scientific and Technical Information Office.
Series: NASA technical paper -- 2738.
Publisher: National Aeronautics and Space Administration, Scientific and Technical Information Office; For sale by the National Technical Information Service]
Published: 1987
Place of publication: [Washington, D.C.]; [Springfield, Va
Language: eng
Format: Microform
Subjects: Electronic digital computers -- Evaluation.
Notes: Distributed to depository libraries in microfiche.

Microfiche. [Washington, D.C.? : National Aeronautics and Space Administration], 1987. 1 microfiche.