Transactional memory
By: Tim Harris, James Larus, Ravi Rajwar
Contributors: Larus, James R.; Rajwar, Ravi
Edition: 2nd ed.
Series: Synthesis lectures on computer architecture -- # 11
Publisher: Morgan & Claypool
Published: 2010
Place of publication: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA)
Language: eng
Format: [electronic resource] /
ISBN-13: 9781608452361; 9781608452354
Subjects: Threads (Computer programs); Synchronization; Transaction systems (Computer systems); Parallel programming (Computer science)
Other titles: Synthesis digital library of engineering and computer science.
Description: The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs.This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically - either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, to a language runtime system, or to hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early spring 2010.
Notes: Part of: Synthesis digital library of engineering and computer science.

Title from PDF t.p. (viewed on June 4, 2010).

Series from website.

Includes bibliographical references (p. 209-244).

Abstract freely available; full-text restricted to subscribers or individual document purchasers.

Also available in print.

Mode of access: World Wide Web.

System requirements: Adobe Acrobat Reader.
Table of contents: title: 1. Introduction; title: Motivation; title: Difficulty of Parallel Programming; title: Parallel Programming Abstractions; title: Database Systems and Transactions; title: What Is a Transaction; title: Transactional Memory; title: Basic Transactional Memory; title: Building on Basic Transactions; title: Software Transactional Memory; title: Hardware Transactional Memory; title: What is Transactional Memory Good For; title: Differences Between Database Transactions and TM; title: Current Transactional Memory Systems and Simulators; title: 2. Basic Transactions; title: TM Design Choices; title: Concurrency Control; title: Version Management; title: Conflict Detection; title: Semantics of Transactions; title: Correctness Criteria for Database Transactions; title: Consistency During Transactions; title: Problems with Mixed-Mode Accesses; title: Handling Mixed-Mode Accesses: Lock-Based Models; title: Handling Mixed-Mode Accesses: TSC; title: Nesting; title: Performance, Progress and Pathologies; title: Progress Guarantees; title: Conflict Detection and Performance; title: Contention Management and Scheduling; title: Reducing Conflicts Between Transactions; title: Higher-Level Conflict Detection; title: Summary; title: 3. Building on Basic Transactions; title: Basic Atomic Blocks; title: Semantics of Basic Atomic Blocks; title: Building Basic Atomic Blocks Over TM; title: Providing Strong Guarantees Over Weak TM Systems; title: Extending Basic Atomic Blocks; title: Condition Synchronization; title: Exceptions and Failure Atomicity; title: Integrating Non-TM Resources; title: Binary Libraries; title: Storage Allocation and GC; title: Existing Synchronization Primitives; title: System Calls, IO, and External Transactions; title: Programming with TM; title: Debugging and Profiling; title: TM Workloads; title: User Studies; title: Alternative Models; title: Transactions Everywhere; title: Lock-Based Models over TM; title: Speculation over TM; title: Summary; title: 4. Software Transactional Memory; title: Managing STM Logs and Metadata; title: Maintaining Metadata; title: Undo-Logs and Redo-Logs; title: Read-Sets and Write-Sets; title: Lock-Based STM Systems with Local Version Numbers; title: Two-Phase Locking with Versioned Locks; title: Optimizing STM Usage; title: Providing Opacity; title: Discussion; title: Lock-Based STM Systems with a Global Clock; title: Providing Opacity Using a Global Clock; title: Timebase Extension; title: Clock Contention vs False Conflict Tradeoffs; title: Alternative Global Clock Algorithms; title: Lock-Based STM Systems with Global Metadata; title: Bloom Filter Conflict Detection; title: Value-Based Validation; title: Nonblocking STM Systems; title: Per-object Indirection; title: Nonblocking Object-Based STM Design Space; title: Nonblocking STM Systems Without Indirection; title: Additional Implementation Techniques; title: Supporting Privatization Safety and Publication Safety; title: Condition Synchronization; title: Irrevocability; title: Distributed STM Systems; title: STM for Clusters; title: STM-Based Middleware; title: STM for PGAS Languages; title: STM Testing and Correctness; title: Summary; title: 5. Hardware-Supported Transactional Memory; title: Basic Mechanisms for Conventional HTMs; title: Identifying Transactional Locations; title: Tracking Read-Sets and Managing Write-Sets; title: Detecting Data Conflicts; title: Resolving Data Conflicts; title: Managing Architectural Register State; title: Committing and Aborting HTM Transactions; title: Conventional HTM Proposals; title: Explicitly Transactional HTMs; title: Implicitly Transactional HTM Systems; title: Hybrid TMs: Integrating HTMs and STMs; title: Software and Design Considerations; title: Alternative Mechanisms for HTMs; title: Software-Resident Logs for Version Management; title: Signatures for Access Tracking; title: Conflict Detection via Update Broadcasts; title: Deferring Conflict Detection; title: Unbounded HTMs; title: Combining Signatures and Software-Resident Logs; title: Using Persistent Meta-Data; title: Using Page Table Extensions; title: Exposing Hardware Mechanisms to STMs; title: Accelerating Short Transactions and Filtering Redundant Reads; title: Software Controlled Cache Coherence; title: Exposed Signatures to STMs; title: Exposing Metadata to STMs; title: Extending HTM: Nesting, IO, and Synchronization; title: Summary; title: 6. Conclusions; title: Bibliography; title: Authors' Biographies.