Designing logic systems using state machines
By: [by] Christopher R. Clare.
Publisher: McGraw-Hill
Published: 1973
Place of publication: New York
Language: eng
Number of pages: 116
Subjects: Electronic digital computers -- Design and construction.; Digital electronics.
First sentence: Deciding where to begin must plague every person who decides to describe anything, and this author for one is no different.
Description: Describes the fundamentals of state-machine design with an emphasis on using state machines to stress the importance of modular design, as well as for determining behavior and implementing the design.
Notes: Includes bibliographies.
Table of contents: label: I
title: Introductory Concepts
pagenum: 1; label: 1.0
title: Where to Begin
pagenum: 1; label: 1.1
title: Basic Design Concepts in Logic
pagenum: 1; label: 1.2
title: Functional Paretitioning
pagenum: 1; label: 1.3
title: Describing a Task with an Algorithm
pagenum: 2; label: II
title: The Module Definition
pagenum: 7; label: 2.0
title: The Definition Phase
pagenum: 7; label: 2.1
title: The State Machine
pagenum: 7; label: 2.2
title: Terminal Definition
pagenum: 8; label: 2.3
title: A Sample Definition
pagenum: 9; label: 2.4
title: Definition Documentation
pagenum: 11; label: III
title: Machine Class Descriptions
pagenum: 13; label: 3.0
title: The Description Phase
pagenum: 13; label: 3.1
title: The Three Classic Description Languages of Logic
pagenum: 13; title: Logic and Boolean Expressions
pagenum: 13; title: Tabular Descriptions
pagenum: 14; title: The Karnaugh Map Description
pagenum: 14; label: 3.2
title: The ASM Chart Description of Logic
pagenum: 16; label: 3.3
title: Machine Classes
pagenum: 20; label: 3.4
title: Class 0 - Combinatorial Logic
pagenum: 20; label: 3.5
title: Class 1 - Delay Machines
pagenum: 22; label: 3.6
title: Class 2 - Direct State Transition and State Output
pagenum: 26; label: 3.7
title: Class 3 - Conditional State Transition and State Output
pagenum: 29; label: 3.8
title: Class 4 - Conditional State Transition and Conditional State Output
pagenum: 30; label: 3.9
title: Summary of Machine Classes
pagenum: 33; label: IV
title: Synthesis for Gate-Oriented Design
pagenum: 35; label: 4.0
title: The Fourth Phase
pagenum: 35; label: 4.1
title: Symbolic Logic Circuits
pagenum: 35; label: 4.2
title: The Synthesis Process
pagenum: 36; label: 4.3
title: Equation-To-Gate Conversions
pagenum: 39; label: 4.4
title: Using Maps to Simplify Boolean Functions
pagenum: 39; title: Map Subcubes and Reading Maps
pagenum: 39; title: Reducing the Required Map Size with Map-Entered Variables
pagenum: 41; title: A Map-Reading Algorithm
pagenum: 42; label: 4.5
title: Output Function Synthesis
pagenum: 43; label: 4.6
title: Multi-Output Simplifications
pagenum: 43; label: 4.7
title: Next State Function Synthesis
pagenum: 44; title: Snthesizing Flip-Flops (Unclocked State Machines)
pagenum: 44; title: Use of the Excitation Table for Flip-Flop Inputs
pagenum: 50; label: 4.8
title: State Assignment
pagenum: 55; title: Minimum State Locus
pagenum: 56; title: Reduced Dependency
pagenum: 57; title: Transition Races
pagenum: 59; title: State Assignment Simplifictions
pagenum: 64; label: 4.9
title: Hazards
pagenum: 65; label: 4.10
title: Simple Implementation
pagenum: 66; label: V
title: Synthesis for ROM-Centered Deisgn
pagenum: 75; label: 5.0
title: The Read Only Memory
pagenum: 75; label: 5.1
title: A ROM Structure as Combinatorial Logic
pagenum: 75; label: 5.2
title: Sequential Logic in ROMs
pagenum: 76; title: Link-Path Addressable
pagenum: 77; title: State-Qualifier Pair Addresses
pagenum: 80; title: Assumed Addresses
pagenum: 80; title: Variable Format Addressable
pagenum: 80; label: 5.3
title: Information Storage Reduction
pagenum: 84; title: Coding Efficiency
pagenum: 84; title: Bit Packing
pagenum: 86; title: Function Extraction
pagenum: 87; title: Changeability and Compaction
pagenum: 87; label: 5.4
title: Comparative Implementations
pagenum: 87; label: VI
title: Linked State Machines
pagenum: 97; label: 6.0
title: Linked State Machines
pagenum: 97; label: 6.1
title: Interface Linking
pagenum: 97; label: 6.2
title: Iteratively Linked Machines
pagenum: 98; title: Adders
pagenum: 98; title: Ripple Counters
pagenum: 100; title: Shift Registers
pagenum: 101; label: 6.3
title: Interpretively Linked Machines
pagenum: 101; title: Levels and Total State
pagenum: 101; title: Interpreted Outputs
pagenum: 103; title: Computer Structures
pagenum: 105; label: 6.4
title: Software Linked Machines
pagenum: 107; label: 6.5
title: Conclusion
pagenum: 107; label: VII
title: Introduction to Peformance Evaluation
pagenum: 109; label: 7.0
title: Performance Evaluation
pagenum: 109; label: 7.1
title: Simulation
pagenum: 109; label: 7.2
title: Test
pagenum: 111; label: 7.3
title: Design for Test
pagenum: 113; title: Index
pagenum: 115