A 20 GHz silicon germanium-HBT phase locked loop (PLL) for serial link applications.
Published: 2005
Language: eng
Number of pages: 122
Description: The PLL proposed in this thesis is based on an inductorless single-stage ring-type VCO, using a diode bridge doubling method to achieve 20 GHz oscillation frequency in the 47 GHz technology. Self injection locking (SIL), is used for the first time in the design of the VCO. A modified Gilbert cell is used as the phase detector and parasitic components are used as the low pass filter in the PLL.Demand for higher data rate network connections and the expansion of multi-media applications in new generation cellular phones, have increased the need for economical high-speed serial transceivers. An important block in the transceiver is the PLL that plays a major role in both the transmitter and the receiver. This thesis deals with the design and implementation of an inductorless high-speed PLL in a 0.5 mum BiCMOS SiGe-HBT process technology with a unity gain cut off frequency of 47 GHz.The frequency range of the implemented PLL is 12--20 GHz which renders it suitable for 20 and 40 Gb/s systems. The PLL exhibits a phase noise of better than -103 dBc/Hz at 1 MHz offset which translates to near 0.13 ps rms jitter. The total power dissipation of the chip is 221 mW from a single -3.3 V power supply and its area occupied is less than 0.2 mm2. The proposed PLL architecture also has the potential for use in 80 Gb/s serial-links.
Notes: Thesis (Ph.D.)--University of Toronto, 2005.

Electronic version licensed for access by U. of T. users.

Source: Dissertation Abstracts International, Volume: 66-06, Section: B, page: 3327.
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