IEEE standard definitions and characterization of floating gate semiconductor arrays
By: Sponsor, Standards Committee of the IEEE Electron Devices Society.
Contributors: IEEE Electron Devices Society. Standards Committee.; Institute of Electrical and Electronics Engineers.; IEEE-SA Standards Board.
Series: IEEE STd -- 1005-1998.; IEEE std -- 1005-1998.
Publisher: Institute of Electrical and Electronics Engineers
Published: 1999
Place of publication: New York, N.Y., USA
Language: eng
Number of pages: 123
Subjects: Semiconductor storage devices -- Standards; Integrated circuits -- Very large scale integration -- Testing
Other titles: Standard definitions and characterization of floating gate semiconductor arrays.
Description: This standard describes the underlying physics and the operation of floating gate memory arrays, specifically, UV erasable EPROM, byte rewritable E²PROMs, and block rewritable "flash" EEPROMs. In addition, reliability hazards are covered with focus on retention, endurance, and disturb. There are also clauses on the issues of testing floating gate arrays and their hardness to ionizing radiation.
Notes: "IEEE 1005-1998, revision of IEEE Std 1005-1991."

"Approved 25 June 1998; IEEE-SA Standards Board."

Includes bibliographical references (p. 117-123).