The design and analysis of instruction set processors
By: Mario R. Barbacci, Daniel P. Siewiorek.
Contributors: Siewiorek, Daniel P.
Series: McGraw-Hill computer science series
Publisher: McGraw-Hill
Published: 1982
Place of publication: New York
Language: eng
Number of pages: 243
Subjects: Computer architecture.; ISP (Computer program language)
Notes: Bibliography: p. 237-238.
Includes index.
Table of contents: label: 1
title: The ISPS Notation
pagenum: 1; label: 1.1
title: Instruction Set Processor Descriptions
pagenum: 1; title: Memory State
pagenum: 1; title: Processor State
pagenum: 2; title: Instruction Format
pagenum: 2; title: Partitioning the Description
pagenum: 3; label: 1.2
title: Effective Address
pagenum: 4; title: Address Computation
pagenum: 4; title: Indirect Addresses
pagenum: 5; title: Auto Indexing
pagenum: 5; label: 1.3
title: Instruction Interpretation
pagenum: 6; title: Operation Code 0\AND: Logical And
pagenum: 7; title: Operation Code 1\TAD: Two's Complement Add
pagenum: 7; title: Operation Code 2\ISZ: Increment and Skip if Zero
pagenum: 7; title: Operation Code 3\DCA: Deposit and Clear Accumulator
pagenum: 8; title: Operation Code 4\JMS: Jump to Subroutine
pagenum: 8; title: Operation Code 5\JMP: Jump
pagenum: 8; title: Operation Code 6\iot: Input/Output
pagenum: 8; title: Operation Code 7\opr: Operate
pagenum: 9; label: 1.4
title: Other Features of ISPS
pagenum: 9; title: Constants
pagenum: 9; title: Arithmetic Representation
pagenum: 10; title: Sign Extension
pagenum: 11; title: Data Operators (in order of precedence)
pagenum: 11; title: Control Operators
pagenum: 12; title: Predeclared Procedures
pagenum: 12; label: 1.5
title: Summary and Writing Conventions
pagenum: 14; label: 2
title: Data Types and Operators
pagenum: 15; label: 2.1
title: Basic Units
pagenum: 15; label: 2.2
title: Data Structures
pagenum: 23; label: 2.3
title: Problems
pagenum: 24; label: 3
title: Instruction Formats
pagenum: 29; label: 3.1
title: Instruction Format Components
pagenum: 29; title: n-address Instructions
pagenum: 30; title: 1-address Instructions
pagenum: 31; title: 0-address Instructions
pagenum: 31; title: General Register Instructions
pagenum: 31; title: Next Instruction Address
pagenum: 32; label: 3.2
title: Addressing Modes
pagenum: 32; title: Direct Addressing
pagenum: 33; title: Immediate Addressing
pagenum: 33; title: Indirect Addressing
pagenum: 34; title: Index Addressing
pagenum: 34; title: Self-Modifying Indexing Modes
pagenum: 35; title: Other Addressing Modes
pagenum: 36; label: 3.3
title: Examples of Instruction Formats
pagenum: 38; title: Mark-1
pagenum: 39; title: PDP-8
pagenum: 40; title: CDC 6600
pagenum: 41; title: System/370
pagenum: 42; title: PDP-11
pagenum: 44; label: 3.4
title: Problems
pagenum: 47; label: 4
title: Memory Management
pagenum: 49; label: 4.1
title: Bank Switching
pagenum: 49; label: 4.2
title: Segmentation and Paging
pagenum: 51; title: Burroughs B 5000
pagenum: 51; title: DEC PDP-11
pagenum: 55; title: IBM System/370
pagenum: 58; label: 4.3
title: Implementation Techniques
pagenum: 61; label: 4.4
title: Problems
pagenum: 62; label: 5
title: Control and Programming Techniques
pagenum: 63; label: 5.1
title: Arithmetic Exceptions, Condition Codes, Skip/Branch/Jump Instructions
pagenum: 64; label: 5.2
title: Loop Control
pagenum: 68; label: 5.3
title: Subroutines and Coroutines
pagenum: 69; label: 5.4
title: Operating System Calls, Traps, Faults, Aborts
pagenum: 71; label: 5.5
title: Problems
pagenum: 73; label: 6
title: Input/Output Organization
pagenum: 75; label: 6.1
title: Program Controlled Input/Output
pagenum: 77; label: 6.2
title: Interrupt Controlled Input/Output
pagenum: 80; title: PDP-8
pagenum: 80; title: System/370
pagenum: 81; title: PDP-11
pagenum: 84; title: Related Topics
pagenum: 86; label: 6.3
title: Problems
pagenum: 87; label: 7
title: Design of Instruction Sets
pagenum: 89; label: 7.1
title: Address Space Size
pagenum: 90; label: 7.2
title: Instruction Format: Addresses, Operators, Expansion, and Compatibility
pagenum: 90; label: 7.3
title: Symmetry, Orthogonality, and Generality
pagenum: 92; label: 7.4
title: Miscellaneous
pagenum: 95; label: 7.5
title: Problems
pagenum: 100; label: 8
title: Evaluation of Computer Architectures
pagenum: 105; label: 8.1
title: The Computer Family Architecture Project
pagenum: 105; label: 8.2
title: Absolute Criteria
pagenum: 106; label: 8.3
title: Quantitative Criteria
pagenum: 108; title: Normalization of the Quantitative Criteria
pagenum: 115; title: Example
pagenum: 117; label: 8.4
title: Benchmarks
pagenum: 121; label: 8.5
title: Problems
pagenum: 123; label: I
title: Mark-1 ISPS Description
pagenum: 127; label: I.1
title: Mp State
pagenum: 127; label: I.2
title: Pc State
pagenum: 127; label: I.3
title: Instruction Format
pagenum: 127; label: I.4
title: Instruction Execution
pagenum: 127; label: II
title: PDP-8 ISPS Description
pagenum: 129; label: II.1
title: Mp State
pagenum: 129; label: II.2
title: Pc State
pagenum: 129; label: II.3
title: Instruction Format
pagenum: 129; label: II.4
title: Address Calculation
pagenum: 130; label: II.5
title: Interpretation Process
pagenum: 130; label: II.6
title: Instruction Set
pagenum: 130; label: III
title: PDP-11 ISPS Description
pagenum: 133; label: III.1
title: Mp State
pagenum: 134; label: III.2
title: Pc State
pagenum: 134; label: III.3
title: Memory Management
pagenum: 135; label: III.4
title: Implementation Declarations
pagenum: 136; label: III.5
title: Instruction Format
pagenum: 136; label: III.6
title: Address Calculation
pagenum: 137; label: III.7
title: Service Facilities
pagenum: 139; label: III.8
title: Instruction Interpretation
pagenum: 145; label: III.9
title: Instruction Execution
pagenum: 145; label: III.10
title: Integer Extended Op Codes
pagenum: 154; label: III.11
title: FP11C Floating Point Processor
pagenum: 156; label: III.12
title: Floating Point Processor State
pagenum: 156; label: III.13
title: Floating Point Implementation Declarations
pagenum: 156; label: III.14
title: Floating Point Instruction Format
pagenum: 157; label: III.15
title: Floating Point Service Facilities
pagenum: 157; label: III.16
title: Floating Point Instruction Execution
pagenum: 161; label: IV
title: System/370 ISPS Description
pagenum: 169; label: IV.1
title: Mp State
pagenum: 169; label: IV.2
title: Pc State
pagenum: 170; label: IV.3
title: Implementation Declarations
pagenum: 171; label: IV.4
title: Instruction Format
pagenum: 172; label: IV.5
title: Address Calculation
pagenum: 172; label: IV.6
title: Service Facilities
pagenum: 174; label: IV.7
title: Floating Point Operators
pagenum: 179; label: IV.8
title: Instruction Interpretation
pagenum: 181; label: IV.9
title: Instruction Decoding
pagenum: 182; label: IV.10
title: Instruction Execution
pagenum: 187; label: V
title: CDC 6600 Central Processor ISPS Description
pagenum: 215; label: V.1
title: Central Memory State
pagenum: 216; label: V.2
title: Processor State
pagenum: 216; label: V.3
title: Instruction Format
pagenum: 216; label: V.4
title: Reservation Control State
pagenum: 216; label: V.5
title: Reservation Control
pagenum: 217; label: V.6
title: Instruction Fetch
pagenum: 219; label: V.7
title: Central Memory Access
pagenum: 220; label: V.8
title: Exchange Jump
pagenum: 221; label: V.9
title: Instruction Cycle
pagenum: 222; label: V.10
title: Branch Unit
pagenum: 223; label: V.11
title: Boolean Unit
pagenum: 224; label: V.12
title: Shift Unit
pagenum: 224; label: V.13
title: Add Unit
pagenum: 225; label: V.14
title: Long Add Unit
pagenum: 226; label: V.15
title: Multiply Unit 0
pagenum: 226; label: V.16
title: Multiply Unit 1
pagenum: 226; label: V.17
title: Divide Unit
pagenum: 227; label: V.18
title: Increment Unit 0
pagenum: 227; label: V.19
title: Increment Unit 1
pagenum: 229; label: VI
title: CDC 6600 Peripheral Processor ISPS Description
pagenum: 231; label: VI.1
title: Channel State
pagenum: 231; label: VI.2
title: Barrel State
pagenum: 231; label: VI.3
title: PCP Memory State
pagenum: 231; label: VI.4
title: PCP Instruction Format
pagenum: 231; label: VI.5
title: Addressing Calculation
pagenum: 232; label: VI.6
title: Barrel Execution
pagenum: 232; label: VI.7
title: PCP Execution
pagenum: 232; title: References
pagenum: 237; title: Index
pagenum: 239