The minimization of multiple valued logic expressions using parallel processors
Contributors: Yang, Chyan; Butler, Jon T.; Schoenstadt, Arthur L.
Publisher: Naval Postgraduate School; Available from the National Technical Information Service
Published: 1991
Place of publication: Monterey, Calif; Springfield, Va
Language: eng
Number of pages: 117
Notes: Thesis advisors, Chyan Yang, Jon T. Butler and Arthur L. Schoenstadt.

AD-A245 763.

Thesis (M.S. in Electrical Engineering and M.S. in Systems Engineering (Electronic Warfare)) Naval Postgraduate School, Sept. 1991.

Includes bibliographical references.