Wafer-level testing and test during burn-in for integrated circuits / Sudarshan Bahukudumbi, Krishnendu Chakrabarty
Contributors: Chakrabarty, Krishnendu
Series: Artech House integrated microsystems series
Publisher: Artech House
Published: 2010
Place of publication: Boston
Language: eng
Number of pages: 198
ISBN-13: 9781596939899
Description: Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert insights on current industry trends in WLTBI test solutions.
Notes: Includes bibliographical references and index.