High Performance Sub-Sampling Phase Detector based Ring-Oscillator Phase-Locked Loops
By: Shravan Siddartha Nagam
Publisher: [publisher not identified]
Published: 2020
Place of publication: [New York, N.Y.?]
Language: eng
Description: Phase locked loops (PLLs) used to generate high precision clocks are integral components in the majority of modern day electronic systems such as Analog-to-Digital Converters (ADC), Digital-to-Analog Converters (DAC), transceivers, processors, etc. The accuracy of this clocks that effects the overall performance of the system is measured in terms of its jitter, phase noise, spurious tones, etc. For example, the jitter in an ADC sampling clock can result in uncertainty of the sampling instant and can result in degradation of the effective number of bits (ENOB) of the ADC, phase noise on the other hand can result in reciprocal mixing in receivers and leakage into adjacent channels in transmitters. Therefore it is very desirable to design PLLs that generate clean clocks with minimal area and power consumption. This thesis discusses two PLL prototypes in 65nm CMOS technology. The first prototype demonstrates a sub-sampling phase detector (SSPD) based feed-forward noise cancellation (FFNC) scheme in a Type-II ring oscillator (RO) PLL.

The FFNC technique uses the already available noise information at the SSPD output and cancels it from the PLL output. The proposed FFNC achieves a 1.4x reduction in jitter, 19.5dB power supply induced noise suppression at the PLL output while consuming a small area of 0.022mm2. The second prototype demonstrates a Type-I SSPD based RO PLL. The SSPD sample-and-hold action generates a steady-state voltage to tune the VCO directly. This eliminates the issue of high reference spurs generally associated with a Type-I PLL. Also the Type-I PLL occupies a very low area of 0.008mm2 as it avoids the usage of bulky integrating capacitor generally used in a Type-II PLL. The PLL with 2.4GHz output achieves a phase noise of -122.6dBc/Hz at a 1MHz offset and the power consumption is 6.1mW. It achieves reference spurs of -64.2dBc, RMSjitter of 422fs and FoMjitter of -239.7dB. In addition to the two prototypes, a theoretical discussion on an auxiliary FFNC (AFFNC) cancellation scheme that can work with a generic Type-II RO PLL is also included.

The AFFNC technique uses a stand alone SSPD to extract and cancel noise from the VCO output. The SSPD is embedded into an alignment loop for proper noise extraction and cancellation. Along with AFFNC, which uses one reference edge for noise extraction, a Double Sampled AFFNC (DS-AFFNC) which utilizes both the rising and falling edge of the reference for noise extraction is also included. By using both the reference edges, higher cancellation BW is achieved.
Notes: Department: Electrical Engineering.

Thesis advisor: Peter R. Kinget.

Thesis (Ph.D.)--Columbia University, 2020.