High-Level System Modeling
Subtitle: Specification Languages
By: edited by Jean-Michel Bergé, Oz Levia, Jacques Rouillard
Contributors: Levia, Oz; Rouillard, Jacques
Series: Current Issues in Electronic Modeling -- 3; Current issues in electronic modeling -- 3.
Publisher: Springer US
Published: 1995
Place of publication: Boston, MA
Language: eng
Format: [electronic resource] :
Number of pages: 162
ISBN-13: 9781461359739; 9781461523031
Subjects: Systems engineering; Computer engineering; Computer-aided design; Computer hardware; Electronic data processing; Engineering
Description: The process of modeling hardware involves a certain duality: a model may specify and represent the desires and constraints of the designer, or it may imitate something that already exists, and can end in simulation or documentation. Surprisingly enough, one of the main qualities of a specification formalism is its ability to ignore issues that do not belong to this level. Such formalisms are obviously intended for the first stages of a design, but can also be used in the process of redesign. Having a proper level of description thus avoids two symmetric problems: Overspecification, which would introduce new instances of the hardware constraints that were only meaningful to the previous ones; Underspecification, which would lead to unnecessary work and sometimes to starting again from scratch. £/LIST£ High-Level System Modeling: Specification Languages describes the state-of-the-art in specification formalisms in electronic design. The book provides an overview of object- oriented methodologies. It goes on to highlight several formalisms such as VSPEC, ESTELLE, SDL and LOTOS with methods that map their semantics to simulatable or synthesisable VHDL. Audience: The essential update for researchers, design engineers and technical managers working in design automation and circuit design.
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