Transistor sizing in the design of high-speed CMOS super buffers
By: Gordon R. Steele
Contributors: Naval Postgraduate School (U.S.)
Published: 1988
Language: eng
Number of pages: 132
Subjects: Electrical and computer engineering
Description: An algorithm for sizing transistors for static Complementary-symmetry Metal-Oxide-Semiconductor (CMOS) integrated circuit logic design using silicon gate enhancement mode Field-Effect Transistors (FET) is derived and implemented in software. The algorithm is applied to the mask level hardware design of a three micron minimum feature size p well high-speed super buffer. A software representation of the super buffer can be used for the automated design of custom Very-Large-Scale Integrated (VLSI) circuits. Keywords: MacPITTS; Silicon compiler; CMOS; VLSI; Super buffer; Transistor sizing; and High-Speed CMOS. (rh)
Notes: Thesis advisor(s): Kirk, Donald E. ; Loomis, Herschel H.

"March 1988."

Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, March 1988.

Includes bibliographical references (p. 125-129).

Monterey, California : Naval Postgraduate School ; 1988.

"Approved for public release, distribution unlimited-Cover."

US Marine Corps (USMC) author.