Low-power delta-sigma A/D design for broadband applications.
Published: 2006
Language: eng
Number of pages: 110
ISBN-13: 9780494211311
Description: As a consequence of the scaling of CMOS technology, digital signal processing has become ubiquitous, and digital circuits will continue to benefit from the projected advances in technology. It is not clear however that analog blocks will benefit from further technology scaling. In particularly, A/D converters based on delta sigma (DeltaSigma) modulation are directly subject to the difficulties imposed by the continued scaling of CMOS submicron technology.A second-order low-pass discrete-time delta-sigma modulator using a fully digital feedforward path, which requires an extra quantizer and a digital adder, with an over-sampling ratio of 24 is designed in a 0.18mu m 1P6M CMOS process with availability of MIM caps and deep N-well, suitable for operation from a 1.8V supply voltage. The digital feedforward path reduces the integrators output swing and relaxes the requirements on analog circuits. Implementation nonidealities have been considered carefully in order to define the circuit requirements for a power-efficient CMOS implementation. Extracted simulations of the chip including the pads show a peak SQNR of 77 dB with a sampling frequency of 96MHz. The total analog and digital power consumptions is 7.2mW from 1.8V supply. The chip is going to be tested during the next few months.
Notes: Source: Masters Abstracts International, Volume: 45-03, page: 1602.

Thesis (M.A.Sc.)--University of Toronto, 2006.

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