Design for High Performance, Low Power, and Reliable 3D Integrated Circuits
By: by Sung Kyu Lim
Contributors: SpringerLink (Online service)
Publisher: Springer New York; Imprint: Springer
Published: 2013
Place of publication: New York, NY
Language: eng
Format: [electronic resource] /
Number of pages: 560
ISBN-13: 9781441995421
Subjects: Systems engineering; Engineering; Processor Architectures; Circuits and Systems; Nanotechnology and Microengineering; Computer science
Description: <p>This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits.  It includes details of numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs.  Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process.</p><ul><li>Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability.</li><li>Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the electro-migration failure mechanisms in TSVs.</li><li>Covers design-for-thermal-reliability in 3D ICs, including thermal-aware architectural floorplanning, gate-level placement techniques to alleviate thermal problems, and co-design and co-analysis of thermal, power delivery, and performance.</li><li>Includes issues affecting design-for-mechanical-reliability in 3D ICs, such as the co-efficient of thermal expansion (CTE) mismatch between TSV and silicon substrate, device mobility and full-chip timing variations, and the impact of package elements.</li></ul>
Table of contents: title: Regular vs Irregular TSV Placementfor 3D IC; title: Steiner Routingfor 3D IC; title: Buffer Insertion for 3D IC.-  Low Power Clock Routing for 3D IC; title: Power Delivery Network Design for 3D IC; title: 3D Clock Routing for Pre-bond Testability; title: TSV-to-TSV Coupling Analysis and Optimization; title: TSV Current Crowding and Power Integrity; title: Modeling of Atomic Concentration at the Wire-to-TSV Interface; title: Multi-Objective Archetectural Floorplanning for 3D IC; title: Thermal-aware Gate-level Placement for 3D IC; title: 3D IC Cooling with Micro-Fluidic Channels; title: Mechanical Reliability Analysis and Optimization for 3D IC; title: Impact of Mechanical Stress on Timing Variation for 3D IC; title: Chip/Package Co-Analysis of Mechanical Stress for 3D IC; title: 3D Chip/Packaging Co-Analysis of Stress-Induced Timing Variations; title: TSV Interfracial Crack Analysis and Optimization; title: Ultra High Logic Designs Using Monolithic 3D Integration; title: Impact of TSV Scaling on 3D IC Design Quality; title: 3D-MAPS: 3DMassively Parallel Processor with Stacked Memory.