Analog VLSI integration of massive parallel signal processing systems
By: by Peter Kinget and Michiel Steyaert.
Contributors: Steyaert, Michiel, 1959-
Publisher: Kluwer Academic Publishers
Published: 1997
Place of publication: Boston
Language: eng
Number of pages: 228
Subjects: Linear integrated circuits; Parallel processing (Electronic computers); Signal processing -- Digital techniques; Neural networks (Computer science)
Notes: Includes bibliographical references (p. 211-222) and index.
Table of contents: title: List of Symbols, Notations and Abbreviations
pagenum: vii; title: Preface
pagenum: xi; label: 1
title: Analog Parallel Signal Processing
pagenum: 1; label: 1.1
title: Introduction: Biological Information Processing Systems vs Artificial Information Processing Systems
pagenum: 1; label: 1.2
title: Artificial Neural Networks
pagenum: 3; label: 1.3
title: Implementation of Artificial Neural Networks
pagenum: 4; label: 1.4
title: Analog VLSI and Parallel Signal Processing
pagenum: 10; label: 1.5
title: Cellular Neural Networks
pagenum: 12; label: 1.6
title: Conclusions and Scope of This Research
pagenum: 19; label: 2
title: Implications of Mismatch on Analog VLSI
pagenum: 21; label: 2.1
title: Introduction
pagenum: 21; label: 2.2
title: Modeling and Characterization of Transistor Mismatch
pagenum: 23; label: 2.3
title: Implications of Mismatch on Transistor Behavior
pagenum: 35; label: 2.4
title: Implications of Mismatch on Elementary Stages
pagenum: 40; label: 2.5
title: Implications of Mismatch on Analog System Performance
pagenum: 60; label: 2.6
title: Techniques to Reduce Impact of Mismatch
pagenum: 73; label: 2.7
title: Link with Harmonic Distortion
pagenum: 76; label: 2.8
title: Implications for Analog Parallel Signal Processing Systems
pagenum: 78; label: 2.9
title: Conclusions
pagenum: 80; label: 3
title: Implementation Oriented Theory for CNN's
pagenum: 83; label: 3.1
title: Introduction
pagenum: 83; label: 3.2
title: Influences of VLSI Imperfections on Network Operation
pagenum: 86; label: 3.3
title: Random Static Errors
pagenum: 87; label: 3.4
title: Generation of Accuracy Specifications
pagenum: 99; label: 3.5
title: Random Dynamical Errors
pagenum: 101; label: 3.6
title: Systematic Static Errors
pagenum: 108; label: 3.7
title: Systematic Dynamic Errors
pagenum: 111; label: 3.8
title: Noise in CNN's
pagenum: 114; label: 3.9
title: CNN's as Resistive Grids
pagenum: 114; label: 3.10
title: Robust Template Design
pagenum: 115; label: 3.11
title: Conclusions
pagenum: 117; label: 4
title: VLSI Implementation of CNN's
pagenum: 121; label: 4.1
title: Introduction
pagenum: 121; label: 4.2
title: Analog VLSI Implementation of Computation Operations
pagenum: 122; label: 4.3
title: Programmable Weighting of Signals
pagenum: 124; label: 4.4
title: Input-Output (I/O) Circuits
pagenum: 141; label: 4.5
title: VLSI Cell Architecture for CNN-Cell
pagenum: 147; label: 4.6
title: 4×4 Fully Programmable CNN Prototype Chip
pagenum: 157; label: 4.7
title: 20×20 Analog Parallel Array Processor
pagenum: 170; label: 4.8
title: Performance Evaluation with Other Implementations
pagenum: 192; label: 4.9
title: Conclusions
pagenum: 195; label: 5
title: General Conclusions
pagenum: 197; title: Appendices
pagenum: 202; label: Appendix A
title: MOS Transistor Models
pagenum: 203; title: Bibliography
pagenum: 211; title: Index
pagenum: 223