Partial analog equalization and ADC requirements in wired communications.
Published: 2004
Language: eng
Number of pages: 156
Description: High-speed high-resolution analog-to-digital converters (ADC) are one of the major bottlenecks in digital communication systems. Every extra bit requirement in a high-speed flash ADC roughly doubles the silicon area and power consumption of the chip and furthermore, complicates ADC design.This thesis investigates the ADC requirements for wired communication applications and presents an efficient partial analog equalization approach to reduce the front-end ADC resolution requirement. In contrast to a full-analog equalizer, a partial analog equalizer (PAE) partially equalizes the channel and is complemented by a digital equalizer. The contributions of this thesis include three major components: (1) An analytical study elaborates and quantifies the benefit of partial equalization in terms of ADC bit requirements. (2) It is shown that a fairly simple PAE circuit can yield most of the available advantage. (3) An implementation of a high-speed PAE/ADC, combined on a single 1.8-V CMOS chip, is demonstrated and the benefit of 2--3 bits improvement is verified, experimentally. Moreover, the optimization of PAE coefficients and the similarity of 2-tap PAE to an analog first-order decorrelator is investigated. The analytical discussions include studying the benefit of PAE in baseband systems with both feedforward and decision feedback equalizers. Similar benefits of PAE in a passband modulation system is also discussed as an appendix for future research direction.The target application for this thesis is 622 Mb/s over a 300-m coaxial cable for serial digital video data transmissions. The proposed PAE along with a 6-bit 400-MHz flash ADC was designed and fabricated in a 0.18-mum CMOS process. The fabricated chip consumes 106 mW of power with 34-dB SNDR at 250 MHz sampling clock. For a 400-Mb/s data transmission over a 240-m coaxial channel, experimental results showed an error performance improvement equivalent to an 8-bit-ADC system.
Notes: Adviser:  David A. Johns.

Thesis (Ph.D.)--University of Toronto, 2004.

Electronic version licensed for access by U. of T. users.

Source: Dissertation Abstracts International, Volume: 65-10, Section: B, page: 5303.