Improvements in biasing, compensation and design methods of CMOS operational amplifiers.
Published: 2004
Language: eng
Number of pages: 74
Description: This thesis presents a design methodology for CMOS integrated circuits based on the MOSFET gate-transconductance-to-drain-current ratio (gm/I D), and the Advanced Compact MOSFET (ACM) model. The design methodology is more suited to current challenges in analog design than existing methodologies because it allows designers to work in weak, moderate, and strong inversion. Using the design methodology, I show how common circuit specifications can be related to gm/ID of MOSFETs within the opamp.Additionally, I present modifications to constant-gm biasing and Miller-lead compensation that mitigate some of their shortcomings. I describe a new constant-gm bias circuit with improved stability. I also present a lead compensation technique with improved stability over load variations.To demonstrate the circuits and the design methodology, I fabricated a test chip in 0.8mum BiCMOS. Simulation results are presented showing a 75% reduction in compensation capacitance for the constant-gm bias circuit, and a 40&deg; improvement in opamp phase margin.
Notes: Adviser: Khoman Phang.

Thesis (M.A.Sc.)--University of Toronto, 2004.

Electronic version licensed for access by U. of T. users.

Source: Masters Abstracts International, Volume: 42-06, page: 2298.

MICR copy on microfiche (1 microfiche).