Stress management for 3D ICs using through silicon vias
Subtitle: International Workshop on Stress Management for 3D ICs Using Through Silicon Vias, Albany, NY, U.S.A, March 16, 2010, San Francisco, CA, U.S.A., July 13, 2010, Dresden, Germany, October 20, 2010
By: editors, Ehrenfried Zschech ... [et al]
Contributors: Zschech, Ehrenfried; International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2010 : San Francisco, Calif.); International Workshop on Stress Management for 3D ICs Using Through Silicon Vias (2010 : Dresden, Germany)
Series: AIP conference proceedings -- 1378; AIP conference proceedings -- no. 1378.
Publisher: American Institute of Physics
Published: 2011
Place of publication: Melville, N.Y
Language: eng
Number of pages: 175
ISBN-13: 9780735409385
Subjects: Stress relaxation; Congresses; Measurement; Simulation methods; Design and construction; Three-dimensional integrated circuits; Strains and stresses
Notes: Includes bibliographical references and index.
Table of contents: title: White papers; title: Multi-scale modeling; title: Multi-scale materials parameters; title: Multi-scale stress characterization; title: TSV : process characterization and failure analysis.