A 1.8 V 2.5 GHz PLL with on-chip charge pump-based supply regulation.
Published: 2005
Language: eng
Number of pages: 66
Description: This thesis presents a fully integrated PLL with an on-chip low-dropout supply regulation using a capacitive DC-DC converter. The design is implemented in TSMC CMOS 6M/1P 0.18 mum technology with a nominal supply voltage of 1.8 V. A charge pump boosts up the reference voltage to 2.5 V, which is then regulated to provide a 1.5 V supply to the PLL. The regulator has achieved a PSR of >-28 dB in simulation, but the measured result is only -18 dB at best. The 1.5V PLL is designed with a fully differential control path and operates at frequencies ranging from 1.5 GHz to 3 GHz with a currentsteering amplifier based ring oscillator. The PLL achieves a cycle-to-cycle jitter level of 11.1 ps RMS with a quiet supply. After the regulator, a jitter level of 46 ps RMS is achieved with +/-5% 2 MHz square wave on the supply. The total power dissipation is 22 mW for the PLL with the regulator.
Notes: Source: Masters Abstracts International, Volume: 44-01, page: 0470.

Thesis (M.A.Sc.)--University of Toronto, 2005.

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