Layoutabhängige Fehleranalyse und Testsynthese integrierter CMOS Schaltungen
By: Marcel Jacomet.
Edition: 1. Aufl.
Series: Series in microelectronics,; v. 8
Publisher: Hartung-Gorre
Published: 1991
Place of publication: Konstanz
Language: ger
Number of pages: 271
Subjects: Digital integrated circuits -- Design and construction -- Data processing.; Metal oxide semiconductors -- Testing -- Data processing.; Integrated circuits -- Fault tolerance.
Notes: Includes bibliographical references (p. 245-261) and index.
Abstract in English, German, and Romansh.
Originally presented as the author's thesis (doctoral)--Eidgenössische Technische Hochschule Zürich, 1990.