VLSI for neural networks and artificial intelligence
By: edited by José G. Delgado-Frias and William R. Moore
Contributors: International Workshop on Artificial Intelligence and Neural Networks (1992 : Oxford, England)
Publisher: Springer Science+Business Media
Published: 1994
Place of publication: New York
Language: eng
Format: [electronic resource] /
Number of pages: 320
ISBN-13: 9781489913319; 9781489913333
Subjects: Computer Systems Organization and Communication Networks; Large scale integration; Neural networks (Computer science); Congresses; Integrated circuits; Electrical Engineering; Artificial intelligence; Computer Science
Notes: "Proceedings of an International Workshop on Artificial Intelligence and Neural Networks, held September 2-4, 1992, in Oxford, United Kingdom"--Title page verso.

Includes bibliographical references and index.
Table of contents: title: Analog Circuits for Neural Networks; title: Analog VLSI Neural Learning Circuits -A Tutorial; title: An Analog CMOS Implementation of a Kohonen Network with Learning Capability; title: Back-Propagation Learning Algorithms for Analog VLSI Implementation; title: An Analog Implementation of the Boltzmann Machine with Programmable Learning Algorithms; title: A VLSI Design of the Minimum Entropy Neuron; title: A Multi-Layer Analog VLSI Architecture for Texture Analysis Isomorphic to Cortical Cells in Mammalian Visual System; title: Digital Implementations of Neural Networks; title: A VLSI Pipelined Neuroemulator; title: A Low Latency Digital Neural Network Architecture; title: MANTRA: A Multi-Model Neural-Network Computer; title: SPERT: A Neuro-Microprocessor; title: Design of Neural Self-Organization Chips for Semantic Applications; title: VLSI Implementation of a Digital Neural Network with Reward-Penalty Learning; title: Asynchronous VLSI Design for Neural System Implementation; title: Neural Networks on Multiprocessor Systems and Applications; title: VLSI-Implementation of Associative Memory Systems for Neural Information Processing; title: A Dataflow Approach for Neural Networks; title: A Custom Associative Chip Used as a Building Block for a Software Reconfigurable Multi-Network Simulator; title: Parallel Implementation of Neural Associative Memories on RISC Processors; title: Reconfigurable Logic Implementation of Memory-Based Neural Networks: A Case Study of the CMAC Network; title: A Cascadable VLSI Design for GENET; title: Parametrised Neural Network Design and Compilation into Hardware; title: Knowledge Processing in Neural Architecture; title: Two Methods for Solving Linear Equations Using Neural Networks; title: VLSI Machines for Artificial Intelligence; title: Hardware Support for Data Parallelism in Production Systems; title: SPACE: Symbolic Processing in Associative Computing Elements; title: PALM: A Logic Programming System on a Highly Parallel Architecture; title: A Distributed Parallel Associative Processor (DPAP) for the Execution of Logic Programs; title: Performance Analysis of a Parallel VLSI Architecture for Prolog; title: A Prolog VLSI System for Real Time Applications; title: An Extended WAM Based Architecture for OR-Parallel Prolog Execution; title: Architecture and VLSI Implementation of a Pegasus-II Prolog Processor; title: Contributors.