VHDL Modeling for Digital Design Synthesis
By: by Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
Contributors: Tsai, Kevin F.; Liu, Jessie T.; Lin, Eric S.
Publisher: Springer US
Published: 1995
Place of publication: Boston, MA
Language: eng
Format: [electronic resource] /
Number of pages: 356
ISBN-13: 9781461359937; 9781461523437
Subjects: Systems engineering; Engineering; Computer-aided design; Computer engineering
Description: VHDL is a hardware description language that allows the specification of a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. Originally introduced as a hardware description language that permitted the simulation of digital designs, VHDL is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this is that not all of its constructs are useful in synthesis. VHDL has data structures, such as files and pointers, which are useful for simulation but not for actual synthesis. As a result, synthesis tools accept only subsets of VHDL. VHDL Modeling for Digital Design Synthesis covers the synthesis aspects of VHDL, keeping the simulation specifics to a minimum. Audience: Working professionals as well as graduate or undergraduate students who can use the book to get acquainted with VHDL and to learn how it can be used in modeling or digital design.
Notes: Online full text is restricted to subscribers.

Also available in print.

Mode of access: World Wide Web.