High-Level Power Analysis and Optimization
By: by Anand Raghunathan, Niraj K. Jha, Sujit Dey
Contributors: Jha, Niraj K.; Dey, Sujit
Publisher: Springer US
Published: 1998
Place of publication: Boston, MA
Language: eng
Format: [electronic resource] /
Number of pages: 175
ISBN-13: 9781461374817; 9781461554332
Subjects: Systems engineering; Engineering; Computer-aided design; Computer engineering
Description: High-Level Power Analysis and Optimization presents a comprehensive description of power analysis and optimization techniques at the higher (architecture and behavior) levels of the design hierarchy, which are often the levels that yield the most power savings. This book describes power estimation and optimization techniques for use during high-level (behavioral synthesis), as well as for designs expressed at the register-transfer or architecture level. High-Level Power Analysis and Optimization surveys the state-of-the-art research on the following topics: power estimation/macromodeling techniques for architecture-level designs, high-level power management techniques, and high-level synthesis optimizations for low power. High-Level Power Analysis and Optimization will be very useful reading for students, researchers, designers, design methodology developers, and EDA tool developers who are interested in low-power VLSI design or high-level design methodologies.
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