Introduction to reconfigurable supercomputing
By: Marco Lanzagorta, Stephen Bique, Robert Rosenberg
Contributors: Bique, Stephen; Rosenberg, Robert
Series: Synthesis lectures on computer architecture -- # 9
Publisher: Morgan & Claypool Publishers; Morgan & Claypool
Published: 2010
Place of publication: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA)
Language: eng
Format: [electronic resource] /
Number of pages: 87
ISBN-13: 9781608453375; 9781608453368
Subjects: Adaptive computing systems; Field programmable gate arrays; Supercomputers
Other titles: Synthesis digital library of engineering and computer science.
Description: This book covers technologies, applications, tools, languages, procedures, advantages, and disadvantages of reconfigurable supercomputing using Field Programmable Gate Arrays (FPGAs). The target audience is the community of users of High Performance Computers (HPC) who may benefit from porting their applications into a reconfigurable environment. As such, this book is intended to guide the HPC user through the many algorithmic considerations, hardware alternatives, usability issues, programming languages, and design tools that need to be understood before embarking on the creation of reconfigurable parallel codes.We hope to show that FPGA acceleration, based on the exploitation of the data parallelism, pipelining and concurrency remains promising in view of the diminishing improvements in traditional processor and system design.
Notes: Part of: Synthesis digital library of engineering and computer science.

Title from PDF t.p. (viewed on January 11, 2010).

Series from website.

Includes bibliographical references (p. 83-86).

Abstract freely available; full-text restricted to subscribers or individual document purchasers.

Also available in print.

Mode of access: World Wide Web.

System requirements: Adobe Acrobat reader.
Table of contents: title: Preface; title: Acknowledgments; title: Introduction; title: 1. FPGA technology: 1.1. ASIC vs. FPGA; 1.2. Physical architecture; 1.3. Logic blocks; 1.4. The interconnect; 1.5. Memory and I/O; 1.6. Reconfigurable programming and FPGA configuration; 1.7. Bitstream Synthesis; 1.8. The Xilinx FPGA; 1.9. Summary; title: 2. Reconfigurable supercomputing: 2.1. NRL Cray XD1; 2.2. Cray API; title: 3. Algorithmic considerations: 3.1. Disadvantages; 3.2. Data parallelism, pipelining, and concurrency; 3.3. Algorithmic requirements; 3.4. I/O considerations; 3.5. Loop structure; 3.6. Effective reconfigurable algorithm design; 3.7. Summary; title: 4. FPGA programming languages: 4.1. VHDL; 4.2. DSPLogic; 4.3. Handel-C; 4.4. Mitrion-C; title: 5. Case study: sorting: 5.1. Concurrent Sorts; 5.2. Pipelining bubblesort; 5.3. A 2-way selection sort implementation; 5.4. Parallel bubblesort; 5.5. Counting sort; 5.6. Simulation; 5.7. Memory conventions and interfaces; 5.8. Generating logic and running codes; title: 6. Alternativetechnologies and concluding remarks: 6.1. Alternative technologies; 6.2. Concluding remarks;; title: A. search.c; title: B. search.hcc; title: Biblography; title: Authors' biographies.