An investigation of memory latency reduction using an address prediction buffer
By: by Arthur B. Billingsley, Jr
Contributors: Fouts, Douglas J.
Publisher: Naval Postgraduate School; Available from the National Technical Information Service
Published: 1992
Place of publication: Monterey, Calif; Springfield, Va
Language: eng
Number of pages: 32
Notes: Thesis advisor, Douglas Fouts.

AD-A261 010.

Thesis (Master of Electrical Engineering) Naval Postgraduate School, Dec. 1992.

Bibliography: p. 30-31.