On-chip self-test circuit blocks for high-speed applications.
Published: 2006
Language: eng
Number of pages: 85
ISBN-13: 9780494163382
Description: In this thesis, the advantages of parallel pseudo-random bit sequence (PRBS) generators for high-speed self-test applications are examined. An ultra-low-power, 4-channel 27 - 1 PRBS generator with 60 mW per channel was designed, fabricated and measured to work correctly up to 23 Gb/s. The circuit was based on a 12-Gb/s, 2.5-mW BiCMOS current-mode logic (CML) latch topology, which, to the best of my knowledge, represents the lowest power for a latch operating above 10-Gb/s. The fabricated chip also included an integrated PRBS checker and error counter. Techniques for further power reduction, by eliminating the current source transistor, and speed improvements, by adding inductive peaking, are presented.
Notes: Source: Masters Abstracts International, Volume: 44-06, page: 2920.

Advisor: Sorin P. Voinigescu.

Thesis (M.A.Sc.)--University of Toronto, 2006.

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