Test Resource Partitioning for System-on-a-Chip (FRONTIERS IN ELECTRONIC TESTING Volume 20) (Frontiers in Electronic Testing)
Edition: 1 edition
Publisher: Springer
Published: May 1, 2002
Language: eng
Format: Hardcover
Number of pages: 248
ISBN-13: 9781402071195
Subjects: Electronic devices & materials; General Theory of Computing; Science/Mathematics; Electronics - General; Technology; Electronic Measurements; Integrated Circuits; Technology & Industrial Arts; Plug and play (Computer architecture); Plug and play (Computer archit; Engineering - Electrical & Electronic; Computer Engineering; Electronics - Circuits - Integrated; Computers : Computer Engineering; Technology / Electronics / Circuits / General; Technology / Engineering / Electrical; Technology : Electronics - Circuits - Integrated; Systems on a chip; Computer Architecture - General; Testing
First sentence: Test resource partitioning (TRP) for a system-on-a-chip (SOC) refers to the process of partitioning monolithic test resources, such as the test data set or the top-level test access mechanism (TAM) into sub-components that can be optimized for significant gains in test resource utilization.