Globally asynchronous locally synchronous designs on FPGA.
Published: 2005
Language: eng
Number of pages: 90
Description: The objective of this thesis is to examine how GALS systems can be implemented on current FPGA architectures.Two of the critical components that make up the communication aspect of a GALS system will be examined: local clock generator and asynchronous interface. The designed local clock generator is an on-chip oscillator and can be stopped with an external signal. The asynchronous interface converts two different timing systems into one synchronous system during data transfer.A GALS system is then compared to an equivalent globally synchronous system. Results indicated that GALS systems performed better when the design size was large and there was a lot of data transferred between modules.Using the tabulated results, it can be concluded that GALS advantages cannot be fully exploited with present FPGA architectures. To fully utilize GALS capabilities, the design tool must understand and correctly synthesize GALS circuits.
Notes: Thesis (M.A.Sc.)--University of Toronto, 2005.

Electronic version licensed for access by U. of T. users.

Source: Masters Abstracts International, Volume: 44-01, page: 0461.

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