Use of Monotonic Static Logic in Scaled, Leaky CMOS Technologies
By: Kagan Irez
Publisher: [publisher not identified]
Published: 2015
Place of publication: [New York, N.Y.?]
Language: eng
Description: This dissertation explores the characteristics of Monotonic-Static CMOS and its potential applications in leakage reduction in ultra scaled Bulk-Si technology with significant gate leakage currents. Using test circuits consisting of different configurations of 16-bit lookahead adders, we performed a comparison among static, monotonic static and domino logic in terms of various properties including power, delay, noise margin and area. Comparisons were done over a wide range of possible transistor widths to fully characterize the tradeoffs for each circuit type. Experimental results show that MS-CMOS has potential advantages in some situations in terms of stand-by power, evaluation speed and noise margin in such a technology.
Notes: Department: Electrical Engineering.

Thesis advisor: Charles A. Zukowski.

Thesis (Ph.D.)--Columbia University, 2015.