Design and Optimization of Low-power Level-crossing ADCs
By: Colin Weltin-Wu
Publisher: [publisher not identified]
Published: 2012
Place of publication: [New York, N.Y.?]
Language: eng
Description: This thesis investigates some of the practical issues related to the implementation of level-crossing ADCs in nanometer CMOS. A level-crossing ADC targeting minimum power is designed and measured. Three techniques to circumvent performance limitations due to the zero-crossing detector at the heart of the ADC are proposed and demonstrated: an adaptive resolution algorithm, an adaptive bias current algorithm, and automatic offset cancelation. The ADC, fabricated in 130 nm CMOS, is designed to operate over a 20 kHz bandwidth while consuming a maximum of 8.5 uW. A peak SNDR of 54 dB for this 8-bit ADC demonstrates a key advantage of level-crossing sampling, namely SNDR higher than the classic Nyquist limit.
Notes: Department: Electrical Engineering.

Thesis advisor: Yannis P. Tsividis.

Thesis (Ph.D.)--Columbia University, 2012.