Digital systems testing and testable design
By: Miron Abramovici, Melvin A. Breuer, Arthur D. Friedman.
Contributors: Breuer, Melvin A.; Friedman, Arthur D.
Series: Electrical engineering, communications, and signal processing; Electrical engineering communications and signal processing series.
Publisher: Computer Science Press
Published: 1990
Place of publication: New York, NY
Language: eng
Number of pages: 653
Subjects: Digital integrated circuits -- Testing.; Digital integrated circuits -- Design and construction.
Notes: Includes bibliographical references (p. 644-645) and index.
Table of contents: title: Preface
pagenum: xvii; title: How This Book Was Written
pagenum: xxi; label: 1
title: Introduction
pagenum: 1; label: 2
title: Modeling
pagenum: 9; label: 2.1
title: Basic Concepts
pagenum: 9; label: 2.2
title: Functional Modeling at the Logic Level
pagenum: 10; label: 2.2.1
title: Truth Tables and Primitive Cubes
pagenum: 10; label: 2.2.2
title: State Tables and Flow Tables
pagenum: 13; label: 2.2.3
title: Binary Decision Diagrams
pagenum: 17; label: 2.2.4
title: Programs as Functional Models
pagenum: 18; label: 2.3
title: Functional Modeling at the Register Level
pagenum: 20; label: 2.3.1
title: Basic RTL Constructs
pagenum: 20; label: 2.3.2
title: Timing Modeling in RTLs
pagenum: 23; label: 2.3.3
title: Internal RTL Models
pagenum: 24; label: 2.4
title: Structural Models
pagenum: 24; label: 2.4.1
title: External Representation
pagenum: 24; label: 2.4.2
title: Structural Properties
pagenum: 26; label: 2.4.3
title: Internal Representation
pagenum: 29; label: 2.4.4
title: Wired Logic and Bidirectionality
pagenum: 31; label: 2.5
title: Level of Modeling
pagenum: 32; title: References
pagenum: 35; title: Problems
pagenum: 36; label: 3
title: Logic Simulation
pagenum: 39; label: 3.1
title: Applications
pagenum: 39; label: 3.2
title: Problems in Simulation-Based Design Verification
pagenum: 41; label: 3.3
title: Types of Simulation
pagenum: 42; label: 3.4
title: The Unknown Logic Value
pagenum: 43; label: 3.5
title: Compiled Simulation
pagenum: 46; label: 3.6
title: Event-Driven Simulation
pagenum: 49; label: 3.7
title: Delay Models
pagenum: 52; label: 3.7.1
title: Delay Modeling for Gates
pagenum: 52; label: 3.7.2
title: Delay Modeling for Functional Elements
pagenum: 54; label: 3.7.3
title: Delay Modeling in RTLs
pagenum: 55; label: 3.7.4
title: Other Aspects of Delay Modeling
pagenum: 55; label: 3.8
title: Element Evaluation
pagenum: 56; label: 3.9
title: Hazard Detection
pagenum: 60; label: 3.10
title: Gate-Level Event-Driven Simulation
pagenum: 64; label: 3.10.1
title: Transition-Independent Nominal Transport Delays
pagenum: 64; label: 3.10.2
title: Other Logic Values
pagenum: 71; label: 3.10.2.1
title: Tristate Logic
pagenum: 71; label: 3.10.2.2
title: MOS Logic
pagenum: 72; label: 3.10.3
title: Other Delay Models
pagenum: 74; label: 3.10.3.1
title: Rise and Fall Delays
pagenum: 74; label: 3.10.3.2
title: Inertial Delays
pagenum: 76; label: 3.10.3.3
title: Ambiguous Delays
pagenum: 76; label: 3.10.4
title: Oscillation Control
pagenum: 77; label: 3.11
title: Simulation Engines
pagenum: 79; title: References
pagenum: 84; title: Problems
pagenum: 86; label: 4
title: Fault Modeling
pagenum: 93; label: 4.1
title: Logical Fault Models
pagenum: 93; label: 4.2
title: Fault Detection and Redundancy
pagenum: 95; label: 4.2.1
title: Combinational Circuits
pagenum: 95; label: 4.2.2
title: Sequential Circuits
pagenum: 103; label: 4.3
title: Fault Equivalence and Fault Location
pagenum: 106; label: 4.3.1
title: Combinational Circuits
pagenum: 106; label: 4.3.2
title: Sequential Circuits
pagenum: 108; label: 4.4
title: Fault Dominance
pagenum: 109; label: 4.4.1
title: Combinational Circuits
pagenum: 109; label: 4.4.2
title: Sequential Circuits
pagenum: 110; label: 4.5
title: The Single Stuck-Fault Model
pagenum: 110; label: 4.6
title: The Multiple Stuck-Fault Model
pagenum: 118; label: 4.7
title: Stuck RTL Variables
pagenum: 122; label: 4.8
title: Fault Variables
pagenum: 122; title: References
pagenum: 123; title: Problems
pagenum: 126; label: 5
title: Fault Simulation
pagenum: 131; label: 5.1
title: Applications
pagenum: 131; label: 5.2
title: General Fault Simulation Techniques
pagenum: 134; label: 5.2.1
title: Serial Fault Simulation
pagenum: 134; label: 5.2.2
title: Common Concepts and Terminology
pagenum: 134; label: 5.2.3
title: Parallel Fault Simulation
pagenum: 135; label: 5.2.4
title: Deductive Fault Simulation
pagenum: 139; label: 5.2.4.1
title: Two-Valued Deductive Simulation
pagenum: 140; label: 5.2.4.2
title: Three-Valued Deductive Simulation
pagenum: 145; label: 5.2.5
title: Concurrent Fault Simulation
pagenum: 146; label: 5.2.6
title: Comparison
pagenum: 154; label: 5.3
title: Fault Simulation for Combinational Circuits
pagenum: 155; label: 5.3.1
title: Parallel-Pattern Single-Fault Propagation
pagenum: 156; label: 5.3.2
title: Critical Path Tracing
pagenum: 157; label: 5.4
title: Fault Sampling
pagenum: 167; label: 5.5
title: Statistical Fault Analysis
pagenum: 169; label: 5.6
title: Concluding Remarks
pagenum: 172; title: References
pagenum: 173; title: Problems
pagenum: 177; label: 6
title: Testing for Single Stuck Faults
pagenum: 181; label: 6.1
title: Basic Issues
pagenum: 181; label: 6.2
title: ATG for SSFs in Combinational Circuits
pagenum: 182; label: 6.2.1
title: Fault-Oriented ATG
pagenum: 182; label: 6.2.1.1
title: Common Concepts
pagenum: 189; label: 6.2.1.2
title: Algorithms
pagenum: 196; label: 6.2.1.3
title: Selection Criteria
pagenum: 213; label: 6.2.2
title: Fault-Independent ATG
pagenum: 220; label: 6.2.3
title: Random Test Generation
pagenum: 226; label: 6.2.3.1
title: The Quality of a Random Test
pagenum: 227; label: 6.2.3.2
title: The Length of a Random Test
pagenum: 227; label: 6.2.3.3
title: Determining Detection Probabilities
pagenum: 229; label: 6.2.3.4
title: RTG with Nonuniform Distributions
pagenum: 234; label: 6.2.4
title: Combined Deterministic/Random TG
pagenum: 235; label: 6.2.5
title: ATG Systems
pagenum: 240; label: 6.2.6
title: Other TG Methods
pagenum: 246; label: 6.3
title: ATG for SSFs in Sequential Circuits
pagenum: 249; label: 6.3.1
title: TG Using Iterative Array Models
pagenum: 249; label: 6.3.2
title: Simulation-Based TG
pagenum: 262; label: 6.3.3
title: TG Using RTL Models
pagenum: 264; label: 6.3.3.1
title: Extensions of the D-Algorithm
pagenum: 265; label: 6.3.3.2
title: Heuristic State-Space Search
pagenum: 269; label: 6.3.4
title: Random Test Generation
pagenum: 271; label: 6.4
title: Concluding Remarks
pagenum: 272; title: References
pagenum: 274; title: Problems
pagenum: 281; label: 7
title: Testing for Bridging Faults
pagenum: 289; label: 7.1
title: The Bridging-Fault Model
pagenum: 289; label: 7.2
title: Detection of Nonfeedback Bridging Faults
pagenum: 292; label: 7.3
title: Detection of Feedback Bridging Faults
pagenum: 294; label: 7.4
title: Bridging Faults Simulation
pagenum: 297; label: 7.5
title: Test Generation for Bridging Faults
pagenum: 301; label: 7.6
title: Concluding Remarks
pagenum: 302; title: References
pagenum: 302; title: Problems
pagenum: 302; label: 8
title: Functional Testing
pagenum: 305; label: 8.1
title: Basic Issues
pagenum: 305; label: 8.2
title: Functional Testing Without Fault Models
pagenum: 305; label: 8.2.1
title: Heuristic Methods
pagenum: 305; label: 8.2.2
title: Functional Testing with Binary Decision Diagrams
pagenum: 309; label: 8.3
title: Exhaustive and Pseudoexhaustive Testing
pagenum: 313; label: 8.3.1
title: Combinational Circuits
pagenum: 313; label: 8.3.1.1
title: Partial-Dependence Circuits
pagenum: 313; label: 8.3.1.2
title: Partitioning Techniques
pagenum: 314; label: 8.3.2
title: Sequential Circuits
pagenum: 315; label: 8.3.3
title: Iterative Logic Arrays
pagenum: 317; label: 8.4
title: Functional Testing with Specific Fault Models
pagenum: 323; label: 8.4.1
title: Functional Fault Models
pagenum: 323; label: 8.4.2
title: Fault Models for Microprocessors
pagenum: 325; label: 8.4.2.1
title: Fault Model for the Register-Decoding Function
pagenum: 327; label: 8.4.2.2
title: Fault Model for the Instruction-Decoding and Instruction-Sequencing Function
pagenum: 328; label: 8.4.2.3
title: Fault Model for the Data-Storage Function
pagenum: 329; label: 8.4.2.4
title: Fault Model for the Data-Transfer Function
pagenum: 329; label: 8.4.2.5
title: Fault Model for the Data-Manipulation Function
pagenum: 329; label: 8.4.3
title: Test Generation Procedures
pagenum: 330; label: 8.4.3.1
title: Testing the Register-Decoding Function
pagenum: 330; label: 8.4.3.2
title: Testing the Instruction-Decoding and Instruction-Sequencing Function
pagenum: 332; label: 8.4.3.3
title: Testing the Data-Storage and Data-Transfer Functions
pagenum: 336; label: 8.4.4
title: A Case Study
pagenum: 337; label: 8.5
title: Concluding Remarks
pagenum: 337; title: References
pagenum: 338; title: Problems
pagenum: 341; label: 9
title: Design for Testability
pagenum: 343; label: 9.1
title: Testability
pagenum: 343; label: 9.1.1
title: Trade-Offs
pagenum: 344; label: 9.1.2
title: Controllability and Observability
pagenum: 345; label: 9.2
title: Ad Hoc Design for Testability Techniques
pagenum: 347; label: 9.2.1
title: Test Points
pagenum: 347; label: 9.2.2
title: Initialization
pagenum: 351; label: 9.2.3
title: Monostable Multivibrators
pagenum: 351; label: 9.2.4
title: Oscillators and Clocks
pagenum: 353; label: 9.2.5
title: Partitioning Counters and Shift Registers
pagenum: 354; label: 9.2.6
title: Partitioning of Large Combinational Circuits
pagenum: 355; label: 9.2.7
title: Logical Redundancy
pagenum: 356; label: 9.2.8
title: Global Feedback Paths
pagenum: 358; label: 9.3
title: Controllability and Observability by Means of Scan Registers
pagenum: 358; label: 9.3.1
title: Generic Boundary Scan
pagenum: 363; label: 9.4
title: Generic Scan-Based Designs
pagenum: 364; label: 9.4.1
title: Full Serial Integrated Scan
pagenum: 365; label: 9.4.2
title: Isolated Serial Scan
pagenum: 366; label: 9.4.3
title: Nonserial Scan
pagenum: 368; label: 9.5
title: Storage Cells for Scan Designs
pagenum: 368; label: 9.6
title: Classical Scan Designs
pagenum: 374; label: 9.7
title: Scan Design Costs
pagenum: 382; label: 9.8
title: Board-Level and System-Level DFT Approaches
pagenum: 382; label: 9.8.1
title: System-Level Busses
pagenum: 383; label: 9.8.2
title: System-Level Scan Paths
pagenum: 383; label: 9.9
title: Some Advanced Scan Concepts
pagenum: 385; label: 9.9.1
title: Multiple Test Session
pagenum: 385; label: 9.9.2
title: Partial Scan Using I-Paths
pagenum: 386; label: 9.9.3
title: BALLAST - A Structured Partial Scan Design
pagenum: 390; label: 9.10
title: Boundary Scan Standards
pagenum: 395; label: 9.10.1
title: Background
pagenum: 395; label: 9.10.2
title: Boundary Scan Cell
pagenum: 398; label: 9.10.3
title: Board and Chip Test Modes
pagenum: 399; label: 9.10.4
title: The Test Bus
pagenum: 401; label: 9.10.5
title: Test Bus Circuitry
pagenum: 402; label: 9.10.5.1
title: The TAP Controller
pagenum: 402; label: 9.10.5.2
title: Registers
pagenum: 407; title: References
pagenum: 408; title: Problems
pagenum: 412; label: 10
title: Compression Techniques
pagenum: 421; label: 10.1
title: General Aspects of Compression Techniques
pagenum: 421; label: 10.2
title: Ones-Count Compression
pagenum: 423; label: 10.3
title: Transition-Count Compression
pagenum: 425; label: 10.4
title: Parity-Check Compression
pagenum: 428; label: 10.5
title: Syndrome Testing
pagenum: 429; label: 10.6
title: Signature Analysis
pagenum: 432; label: 10.6.1
title: Theory and Operation of Linear Feedback Shift Registers
pagenum: 432; label: 10.6.2
title: LFSRs Used as Signature Analyzers
pagenum: 441; label: 10.6.3
title: Multiple-Input Signature Registers
pagenum: 445; label: 10.7
title: Concluding Remarks
pagenum: 447; title: References
pagenum: 448; title: Problems
pagenum: 452; label: 11
title: Built-In Self-Test
pagenum: 457; label: 11.1
title: Introduction to BIST Concepts
pagenum: 457; label: 11.1.1
title: Hardcore
pagenum: 458; label: 11.1.2
title: Levels of Test
pagenum: 459; label: 11.2
title: Test-Pattern Generation for BIST
pagenum: 460; label: 11.2.1
title: Exhaustive Testing
pagenum: 460; label: 11.2.2
title: Pseudorandom Testing
pagenum: 460; label: 11.2.3
title: Pseudoexhaustive Testing
pagenum: 461; label: 11.2.3.1
title: Logical Segmentation
pagenum: 462; label: 11.2.3.2
title: Constant-Weight Patterns
pagenum: 463; label: 11.2.3.3
title: Identification of Test Signal Inputs
pagenum: 466; label: 11.2.3.4
title: Test Pattern Generators for Pseudoexhaustive Tests
pagenum: 471; label: 11.2.3.5
title: Physical Segmentation
pagenum: 476; label: 11.3
title: Generic Off-Line BIST Architectures
pagenum: 477; label: 11.4
title: Specific BIST Architectures
pagenum: 483; label: 11.4.1
title: A Centralized and Separate Board-Level BIST Architecture (CSBL)
pagenum: 483; label: 11.4.2
title: Built-In Evaluation and Self-Test (BEST)
pagenum: 483; label: 11.4.3
title: Random-Test Socket (RTS)
pagenum: 484; label: 11.4.4
title: LSSD On-Chip Self-Test (LOCST)
pagenum: 486; label: 11.4.5
title: Self-Testing Using MISR and Parallel SRSG (STUMPS)
pagenum: 488; label: 11.4.6
title: A Concurrent BIST Architecture (CBIST)
pagenum: 490; label: 11.4.7
title: A Centralized and Embedded BIST Architecture with Boundary Scan (CEBS)
pagenum: 490; label: 11.4.8
title: Random Test Data (RTD)
pagenum: 492; label: 11.4.9
title: Simultaneous Self-Test (SST)
pagenum: 493; label: 11.4.10
title: Cyclic Analysis Testing System (CATS)
pagenum: 495; label: 11.4.11
title: Circular Self-Test Path (CSTP)
pagenum: 496; label: 11.4.12
title: Built-In Logic-Block Observation (BILBO)
pagenum: 501; label: 11.4.12.1
title: Case Study
pagenum: 510; label: 11.4.13
title: Summary
pagenum: 513; label: 11.5
title: Some Advanced BIST Concepts
pagenum: 514; label: 11.5.1
title: Test Schedules
pagenum: 515; label: 11.5.2
title: Control of BILBO Registers
pagenum: 517; label: 11.5.3
title: Partial-Intrusion BIST
pagenum: 520; label: 11.6
title: Design for Self-Test at Board Level
pagenum: 523; title: References
pagenum: 524; title: Problems
pagenum: 532; label: 12
title: Logic-Level Diagnosis
pagenum: 541; label: 12.1
title: Basic Concepts
pagenum: 541; label: 12.2
title: Fault Dictionary
pagenum: 543; label: 12.3
title: Guided-Probe Testing
pagenum: 549; label: 12.4
title: Diagnosis by UUT Reduction
pagenum: 554; label: 12.5
title: Fault Diagnosis for Combinational Circuits
pagenum: 556; label: 12.6
title: Expert Systems for Diagnosis
pagenum: 557; label: 12.7
title: Effect-Cause Analysis
pagenum: 559; label: 12.8
title: Diagnostic Reasoning Based on Structure and Behavior
pagenum: 564; title: References
pagenum: 566; title: Problems
pagenum: 568; label: 13
title: Self-Checking Design
pagenum: 569; label: 13.1
title: Basic Concepts
pagenum: 569; label: 13.2
title: Application of Error-Detecting and Error-Correcting Codes
pagenum: 570; label: 13.3
title: Multiple-Bit Errors
pagenum: 577; label: 13.4
title: Checking Circuits and Self-Checking
pagenum: 578; label: 13.5
title: Self-Checking Checkers
pagenum: 579; label: 13.6
title: Parity-Check Function
pagenum: 580; label: 13.7
title: Totally Self-Checking m/n Code Checkers
pagenum: 581; label: 13.8
title: Totally Self-Checking Equality Checkers
pagenum: 584; label: 13.9
title: Self-Checking Berger Code Checkers
pagenum: 584; label: 13.10
title: Toward a General Theory of Self-Checking Combinational Circuits
pagenum: 585; label: 13.11
title: Self-Checking Sequential Circuits
pagenum: 587; title: References
pagenum: 589; title: Problems
pagenum: 590; label: 14
title: PLA Testing
pagenum: 593; label: 14.1
title: Introduction
pagenum: 593; label: 14.2
title: PLA Testing Problems
pagenum: 594; label: 14.2.1
title: Fault Models
pagenum: 594; label: 14.2.2
title: Problems with Traditional Test Generation Methods
pagenum: 597; label: 14.3
title: Test Generation Algorithms for PLAs
pagenum: 597; label: 14.3.1
title: Deterministic Test Generation
pagenum: 598; label: 14.3.2
title: Semirandom Test Generation
pagenum: 599; label: 14.4
title: Testable PLA Designs
pagenum: 600; label: 14.4.1
title: Concurrent Testable PLAs with Special Coding
pagenum: 600; label: 14.4.1.1
title: PLA with Concurrent Error Detection by a Series of Checkers
pagenum: 600; label: 14.4.1.2
title: Concurrent Testable PLAs Using Modified Berger Code
pagenum: 601; label: 14.4.2
title: Parity Testable PLAs
pagenum: 603; label: 14.4.2.1
title: PLA with Universal Test Set
pagenum: 603; label: 14.4.2.2
title: Autonomously Testable PLAs
pagenum: 605; label: 14.4.2.3
title: A Built-In Self-Testable PLA Design with Cumulative Parity Comparison
pagenum: 606; label: 14.4.3
title: Signature-Testable PLAs
pagenum: 608; label: 14.4.3.1
title: PLA with Multiple Signature Analyzers
pagenum: 609; label: 14.4.3.2
title: Self-Testable PLAs with Single Signature Analyzer
pagenum: 609; label: 14.4.4
title: Partitioning and Testing of PLAs
pagenum: 610; label: 14.4.4.1
title: PLA with BILBOs
pagenum: 611; label: 14.4.4.2
title: Parallel-Testable PLAs
pagenum: 614; label: 14.4.4.3
title: Divide-and-Conquer Strategy for Testable PLA Design
pagenum: 614; label: 14.4.5
title: Fully-Testable PLA Designs
pagenum: 615; label: 14.5
title: Evaluation of PLA Test Methodologies
pagenum: 618; label: 14.5.1
title: Measures of TDMs
pagenum: 618; label: 14.5.1.1
title: Resulting Effect on the Original Design
pagenum: 619; label: 14.5.1.2
title: Requirements on Test Environment
pagenum: 619; label: 14.5.2
title: Evaluation of PLA Test Techniques
pagenum: 620; title: References
pagenum: 627; title: Problems
pagenum: 630; label: 15
title: System-Level Diagnosis
pagenum: 633; label: 15.1
title: A Simple Model of System-Level Diagnosis
pagenum: 633; label: 15.2
title: Generalizations of the PMC Model
pagenum: 638; label: 15.2.1
title: Generalizations of the System Diagnostic Graph
pagenum: 638; label: 15.2.2
title: Generalization of Possible Test Outcomes
pagenum: 640; label: 15.2.3
title: Generalization of Diagnosability Measures
pagenum: 641; title: References
pagenum: 644; title: Problems
pagenum: 645; title: Index
pagenum: 647