Extraction error modelling and automated debugging in high-performance custom designs.
Published: 2004
Language: eng
Number of pages: 95
Description: Test model generation is a crucial step in the design cycle of high performance VLSI circuits. A key step in test model generation is logic extraction, which generates a gate-level netlist from a transistor-level design. Logic extraction is error-prone due to human interference and limitations of the automated extraction tools. Currently, extraction errors require a resource intensive and time consuming manual debugging.This thesis, first, presents a case study of several typical extraction errors found in an industrial environment based on the core circuits used in the PentiumRTM 4 microprocessor. Secondly, it proposes an automated debugging methodology for these extraction errors that occur in strictly pipelined sequential circuits. This circuit structure resembles the architecture of high-speed industrial components found in modern microprocessors. The method is applicable to designs with full, partial and no memory equivalence information. Experimental results confirm the fitness and the advantage of this automated debugging approach.
Notes: Adviser:  A. Veneris.

Thesis (M.A.Sc.)--University of Toronto, 2004.

Electronic version licensed for access by U. of T. users.

Source: Masters Abstracts International, Volume: 43-03, page: 0951.

MICR copy on microfiche (2 microfiches).