Computer Engineering and Technology
Subtitle: 16th National Conference, NCCET 2012, Shanghai, China, August 17-19, 2012, Revised Selected Papers
By: edited by Weixia Xu, Liquan Xiao, Pingjing Lu, Jinwen Li, Chengyi Zhang
Contributors: Xiao, Liquan; Lu, Pingjing; Li, Jinwen; Zhang, Chengyi; SpringerLink (Online service)
Series: Communications in Computer and Information Science -- 337
Publisher: Springer Berlin Heidelberg; Imprint: Springer
Published: 2013
Place of publication: Berlin, Heidelberg
Language: eng
Format: [electronic resource] :
Number of pages: 263
ISBN-13: 9783642358982
Subjects: Processor Architectures; Performance and Reliability; Memory Structures; Logic design; Computer science; Arithmetic and Logic Structures; Memory management (Computer science); Operating systems (Computers)
Description: This book constitutes the refereed proceedings of the 16th National Conference on Computer Engineering and Technology, NCCET 2012, held in Shanghai, China, in August 2012. <br>The 27 papers presented were carefully reviewed and selected from 108 submissions. They are organized in topical sections named: microprocessor and implementation; design of integration circuit; I/O interconnect; and measurement, verification, and others.
Table of contents: title: Session 1: Microprocessor and Implementation; title: A Method of Balancing the Global Multi-mode Clock Network in Ultra-large Scale CPU; title: Hardware Architecture for the Parallel Generation of Long-Period Random Numbers Using MT Method; title: MGTE: A Multi-level Hybrid Verification Platform for a 16-Core Processer; title: An Efficient Parallel SURF Algorithm for Multi-core Processor; title: A Study of Cache Design in Stream Processor; title: Design and Implementation of Dynamically Reconfigurable Token Coherence Protocol for Many-Core Processor; title: Dynamic and Online Task Scheduling Algorithm Based on Virtual Compute Group in Many-Core Architecture; title: ADL and High Performance Processor Design; title: Session 2: Design of Integration Circuit; title: The Design of the ROHC Header Compression Accelerator; title: A Hardware Implementation of Nussinov RNA Folding Algorithm; title: A Configurable Architecture for 1-D Discrete Wavelet Transform; title: A Comparison of Folded Architectures for the Discrete Wavelet Transform; title: ^; title: A High Performance DSP System with Fault Tolerant for Space Missions; title: The Design and Realization of Campus Information Release Platform Based on Android Framework; title: A Word-Length Optimized Hardware Gaussian Random Number Generator Based on the Box-Muller Method; title: Session 3: I/O Interconnect; title: DAMQ Sharing Scheme for Two Physical Channels in High Performance Router; title: Design and Implementation of Dynamic Reliable Virtual Channel for Network-on-Chip; title: HCCM: A Hierarchical Cross-Connected Mesh for Network on Chip; title: Efficient Broadcast Scheme Based on Sub-network Partition for Many-Core CMPs on Gem5 Simulator; title: A Quick Method for Mapping Cores Onto 2D-Mesh Based Networks on Chip; title: Session 4: Measurement, Verification, and Others; title: A Combined Hardware/Software Measurement for ARM Program Execution Time; title: A Low-Complexity Parallel Two-Sided Jacobi Complex SVD Algorithm and Architecture for MIMO Beamforming Systems; title: ^; title: ^^; title: A Thermal-Aware Task Mapping Algorithm for Coarse Grain Reconfigurable Computing System; title: DC Offset Mismatch Calibration for Time-Interleaved ADCs in High-Speed OFDM Receivers; title: An Novel Graph Model for Loop Mapping on Coarse-Grained Reconfigurable Architectures; title: Memristor Working Condition Analysis Based on SPICE Model; title: On Stepsize of Fast Subspace Tracking Methods.; title: ^^