High Level Synthesis of ASICs under Timing and Synchronization Constraints
By: by David C. Ku, Giovanni Micheli
Contributors: Micheli, Giovanni
Series: The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing -- 177; Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing -- 177.
Publisher: Springer US
Published: 1992
Place of publication: Boston, MA
Language: eng
Format: [electronic resource] /
Number of pages: 294
ISBN-13: 9781441951298; 9781475721171
Subjects: Systems engineering; Engineering; Computer-aided design; Computer engineering
Description: Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book. Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model. The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.
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