Implementation of MAC using Modified Booth Algorithm
Publisher: Association of Scientists, Developers and Faculties
Published: 2016
Place of publication: Tiruppur, Tamil Nadu, India
Language: eng
ISBN-13: 9788192986647
Description: The proposed system is an efficient processing of 16-bit Multiplier Accumulator using Radix-8 and Radix-16 modified Booth Algorithm and other adders (SPST adder, Carry select adder, Parallel Prefix adder) using VHDL (Very High Speed Integrated Circuit Hardware Description Language). This proposed system provides low power, high speed and fewer delays. In both booth multipliers, comparison between the power consumption (mw) and estimated delay (ns) are calculated. The application of digital signal processing like fast fourier transform, finite impulse response and convolution needs high speed and low power MAC (Multiplier and Accumulator) units to construct an added. By reducing the glitches (from 1 to 0 transition) and spikes (from 0 to 1 transition), the speed of operation is improved and dynamic power is reduced. The adder designed with SPST avoids the unwanted glitches and spikes, reduce the switching power dissipation and the dynamic power. The speed can be improved by reducing the number of partial products to half, by grouping of bits in the multiplier term.  The  proposed Radix-8 and Radix-16  Modified Booth Algorithm MAC  with SPST  reduces  the  delay and  obtain low  power  consumption  as  compared  to array MAC.