Hardware implementation of recursive fixed-point filters for minimum quantization noise
By: Carlos José de Almeida Rodrigues, Rodolfo
Contributors: Naval Postgraduate School (U.S.). Department of Electrical Engineering
Publisher: Naval Postgraduate School
Published: 1974
Place of publication: Monterey, Calif
Language: eng
Format: Electronic resource
Subjects: Hardware; Shift registers; Logic devices; Noise; Signal processing
Description: Design and implementation of recursive digital filters with f'ixed point arithmetic using special hardware are considered in detail and applied to a mechanization of a second order filter structure with variable coefficients.  Two new methods of performing quantization after arithmetic operations within a digital filter are presented: quantization  after addition and quantization before multiplication. Both methods are shown applicable to hardware implementation of digital filters and offer advantages over the usual quantization after multiplication. Error bounds are derived for these two quantization schemes and compared with the results previously obtained by other authors. It is concluded that the quantization before multiplication is the most suitable for hardware filter implementation. A design modification of the presently  available hardware chips in order to permit round-off or truncation before multiplication is presented.
Notes: Thesis Advisor(s): Parker, Sydney R. ; Second Reader: Powers, V. Michael.

September 1974.

Author(s) subject terms: Digital Filter, Arithmetric Quantization Errors, Hardware Implementation.

Description based on title screen as viewed on September 26, 2011.

Portuguese Navy author.

Thesis (Degree of Electrical Engineer)--Naval Postgraduate School, September 1974.

Includes bibliographical references (leaves 139-141).

Approved for public release, distribution unlimited--Cover.

Also available in print.

Mode of access: World Wide Web.

System requirements: Adobe Acrobat Reader.

record upgraded 9/28/2011 daw