Formal Semantics and Proof Techniques for Optimizing VHDL Models
By: by Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
Contributors: Pandey, Sheetanshu L.; Wilsey, Philip A.
Publisher: Springer US
Published: 1999
Place of publication: Boston, MA
Language: eng
Format: [electronic resource] /
Number of pages: 158
ISBN-13: 9781461373315; 9781461551232
Subjects: Computer hardware; Systems engineering; Engineering; Computer-aided design; Computer engineering
Description: Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions. Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.
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