Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits
By: David M. Russinoff.
Contributors: Langley Research Center.
Series: NASA contractor report -- 191608.; NASA contractor report -- NASA CR-191608.
Publisher: National Aeronautics and Space Administration, Langley Research Center; National Technical Information Service, distributor
Published: 1995
Place of publication: Hampton, Va; [Springfield, Va
Language: eng
Format: Microform
Subjects: Hardware description languages.; Mathematical models.; Program verification (Computers); Protocol (Computers); VHSIC (Circuits)
Other titles: Specification and verification of gate level VHDL models of synchronous and asynchronous circuits.
Notes: Distributed to depository libraries in microfiche.

Shipping list no.: 95-0479-M.

Microfiche. [Washington, D.C. : National Aeronautics and Space Administration, 1995] 1 microfiche.