A power scaleable and low power pipeline ADC using power resettable opamps.
Published: 2004
Language: eng
Number of pages: 135
Description: A 10-bit pipeline Analog-to-Digital Converter (ADC) is designed such that its average power is scaleable with sampling rate over a large variation of sampling rates. Fabricated in CMOS 0.18mum technology, while having an area of 1.21mm2, the ADC uses a novel fast Power Resettable Opamp (PROamp), to achieve power scalability between sampling rates as high as 50Msps (35mW), and as low as 1ksps (15muW), while having 54--56dB of SNDR (at Nyquist) for all sampling rates. A current modulation technique is used to avoid weakly inverted transistors for low bias currents, thus avoiding less accurate simulation, poorer matching, and increased bias sensitivity. The PROamp due to its short power on/off time also affords reduced power consumption in high speed pipeline ADCs, where opamps can be completely powered off when not required. Measured results show an ADC using PROamps has 20--30% less power than an ADC which does not use PROamps.
Notes: Adviser: David A. Johns.

Thesis (M.A.Sc.)--University of Toronto, 2004.

Electronic version licensed for access by U. of T. users.

Source: Masters Abstracts International, Volume: 43-03, page: 0925.

MICR copy on microfiche (2 microfiches).