Xilinx/XilinxTclStore — pull request #367 by luaraneda (2014-12-04 22:50:30+00:00)
Title: Added a user ip_repo refresh when importing a project

A bug was present when running synthesis immediately after sourcing the generated script.
Test design details:
- Manual created top file (verilog)
- Custom ip_core from user ip_repo instantiated.
- No block design files

Errors obtained:
- [Synth 8-285] failed synthesizing module...
- [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details