ucb-bar/chisel — pull request #333 by sdtwigg (2014-11-20 00:41:45+00:00)
Title: Allow for 0 Fills

-> Emits a zero width wire when n=0
--> Currnetly a bug w zero-width wires that causes bizarre behavior in verilog backend when --W0W not on
-> Better error checking for when n is negative