mspsim/mspsim — pull request #38 by atiselsts (2014-11-17 09:40:51+00:00)
Title: allow MSP430 DCO frequency to be up to 9MHz

This is a quick-and-dirty fix for msp430 Series-2 based mote (e.g. Zolertia Z1) clock speed in simulations.

For now, attempts to configure DCO frequency higher than 4.9 MHz in Cooja lead to ACLK speed being reduced to 16384. The outcome is that Contiki system clock on simulated Z1 motes runs twice slower than expected.

Due to some implementation idiosyncrasies, the problem with Z1 clock speed in simulations appeared only after applying this pull request to Contiki: https://github.com/contiki-os/contiki/pull/606 (it fixes a different clock frequency related bug):

Related: issue #35.