ucb-bar/chisel — pull request #307 by ucbjrl (2014-10-23 23:28:42+00:00)
Title:  Fix for #153 - NameIt is way too eager, needs to chill out (in Verilog-backend only).

Node.nameIt currently applies the '_' disambiguation logic even if a node hasn't been named yet. Ignore unnamed nodes under the assumption we will eventually get around to naming them.