devttys0/libmpsse — pull request #1 by contradict (2014-10-11 17:23:37+00:00)
Title: More robust clock divisor generation

Try generating a divisor with both 12MHz and 60MHz system clock, take the result
with the smallest error. This allows many new baud rates, the ones I needed were
in the 2-5MHz range.

Also remove the freq<0 logic. Since freq is an unsigned value, this can never be
true.