vtsuperdarn/VTRST3.5 — pull request #7 by ksterne (2014-09-08 21:44:04+00:00)
Title: Enhancement/fit error checking really ready

Here is a simpler edit to the fitacfex code that won't use rewritten values for the lag table. The bigger issue with the analysis code is when the lag is greater than 100, the make_fitex2 code breaks.

You'll also see edits to check for smsep=0 for both versions of Badlags. In current state, a smsep=0 will cause all of the memory to be gobbled up by these loops.