openrisc/orpsoc-cores — pull request #74 by bluecmd (2014-07-12 14:55:45+00:00)
Title: Add support for AXI4 and AXI4-Lite type busses

This commit introduces convertion between a foreign bus architecture and
Wishbone. By specifying "type=axi4" or "type=axi4-lite" on either a
slave or a master the interconnect will embed convertion cores and
change the output wires to be those of AXI4 / AXI4-Lite.

This is compatible with the "datawidth" directive.