openrisc/orpsoc-cores — pull request #70 by bandvig (2014-07-02 12:36:34+00:00)
Title: Increase number of addressed instructions for ROM

Number of addressed ROM instruction is increased from 16 to 64.
Otherwise there is no enough room for a BOOTROM_SPI_FLASH-like boot.

Note 1.
Actually, I implemented small program on ASM to switch on board (Atlys) LEDs periodically using GPIO. Let's say it was my 1st exercise with OpenRISC. As I'm not very familiar with simulation tools yet I spend about 2 days to found that address mask for ROM just blocks instructions, so my program couldn't be executed completely. The extension of the mask fixes the problem. Perhaps, it makes sense to expand the mask for other boards.

Note 2.
I haven't included the LEDs switching code into updated rom.v because the increased size of ROM leads to that ISE couldn't route default Atlys configuration. So I have to exclude the VGA0, AC97 and PS_x modules from SoC temporary. If somebody is interested in the code, the following is listing for rom.v (other parts under case(adr) must be commented):

/* LEDs round switching
0 : wb_dat_o <= 32'h18000000; // l.movhi r0, 0 // r0 is zero
1 : wb_dat_o <= 32'h18209100; // l.movhi r1, hi(0x9100) // store gpio base address(0x91000000) in R1
2 : wb_dat_o <= 32'ha88000ff; // l.ori r4, r0, 0xFF // configure GPIO pins...
3 : wb_dat_o <= 32'hd8012001; // l.sb 1(r1), r4 // ... as outputs
4 : wb_dat_o <= 32'ha8800001; // l.ori r4, r0, 0x01 // light on LD0...
5 : wb_dat_o <= 32'hd8012000; // l.sb 0(r1), r4 // ... at startup
6 : wb_dat_o <= 32'h184002fa; // l.movhi r2, hi(0x02fa) // R2 - threshold for ~1sec interval counter (2faf080 = 50e6 = IN_CLK)
7 : wb_dat_o <= 32'ha842f080; // l.ori r2, r2, lo(0xf080) // the threshold is 16 times lower than period defined by IN_CLK
8 : wb_dat_o <= 32'hb8420044; // l.srli r2, r2, 4 // 4 instructions per loop and dependacy delays
9 : wb_dat_o <= 32'ha8600000; // sec_cnt_init: l.ori r3, r0, 0 // ~1sec interval counter reset
10 : wb_dat_o <= 32'h9c630001; // sec_cnt_loop: l.addi r3, r3, 1 // counter increment
11 : wb_dat_o <= 32'he4031000; // l.sfeq r3, r2 // check if we have achived 1sec threshold
12 : wb_dat_o <= 32'h0ffffffe; // l.bnf sec_cnt_loop // if not yet - continue update counter
13 : wb_dat_o <= 32'h15000000; // l.nop
14 : wb_dat_o <= 32'hb8840001; // l.slli r4, r4, 1 // light on for next led
15 : wb_dat_o <= 32'hb8640048; // l.srli r3, r4, 8 // cycle on byte owerflow
16 : wb_dat_o <= 32'ha4630001; // l.andi r3, r3, 0x1 // ...
17 : wb_dat_o <= 32'he0841804; // l.or r4, r4, r3 // ...
18 : wb_dat_o <= 32'ha48400ff; // l.andi r4, r4, 0xFF // ...
19 : wb_dat_o <= 32'hd8012000; // l.sb 0(r1), r4 // put to gpio data register
20 : wb_dat_o <= 32'h03fffff5; // l.j sec_cnt_init // count till next second
21 : wb_dat_o <= 32'h15000000; // l.nop
22 : wb_dat_o <= 32'h15000000; // l.nop
*/