openrisc/orpsoc-cores — pull request #67 by fjullien (2014-06-04 14:45:47+00:00)
Title: adv_debug_sys: fix 32 bits wb access in jsp module

Old code depends on address bits [1:0] to be update during
a 8 bits access on a 32 bits bus. The OR1200 does that.

Because it is not in the wishbone specification, we can't rely
on this. For example, mor1kx set address bits [1:0] to "00".

Signed-off-by: Franck Jullien