PaulStoffregen/cores — pull request #22 by duff2013 (2014-05-30 04:36:58+00:00)
Title: fix for 2 and 4MHz

I think was wrong about running from FLL in BLPI and BLPE mode, actually the FLL is disabled when you set MCG_C2_LP.

This how I have it setup:
4-16 MHz runs from the external ref clock (16 MHz BLPE).
2 MHz runs from fast internal ref clock (4 MHz) but the MCG_SC_FCRDIV defaults to divide by 2. So actually we are running at 2MHz (BLPI). That why changed the dividers.

So I did some measurements and even though I confirm that @ 2MHz we are in VLPR its showing a high current measurement (7.5mA). I'm wondering what is consuming the extra power? I used my low power library with this core and I get 1mA and i can't see any difference. i wonder if the mini54 is not going into lowpower mode also? Now the weird thing, i tried running at 24MHz and put the VLPR code in a sketch and it conforms with my library power measurements. I looked at what initializing code could be adding the extra current but can't find anything.