ucb-bar/chisel — pull request #219 by Dolu1990 (2014-05-26 14:22:06+00:00)
Title: Extend clock capabilities

Allow the following
```scala
//Standard chisel
val clockA = new Clock(resetA);
//Create a clock domaine with clockA as clock and resetB as reset
val clockA_with_resetB = Clock(clockA,resetB);
//create clock domaine with current default clock (clk) and resetC
val resetC = Reg(Bool())
resetC := ...
val clk_with_resetC = Clock(null,resetC);
```
Now _reset from Module is not removed, but you never again should not need it.
The why is here : https://groups.google.com/forum/#!topic/chisel-users/dW3hLgie9us

I have try to be the less intrusive possible in chisel code to don't add bugs and border effect.
If you find wrong thing in this pull request, give me feed back, and i do a second iteration.