zjuacompiler/llvm — pull request #19 by laishzh (2014-05-21 17:10:53+00:00)
Title: Legalize v32i1 and make use of pext in haswell

Goal
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I am working on legalizing type v32i1, and transforming vector_shuffle into pext operation in some specific masks.

How
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1. Legalize the type by addRegisterClass and edit file x86RegisterInfo.td to associate the type with proper register.
2. SetOperationAction to overwrite the default action of specific Operation with the type, like
```setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom);```
If you want to use the ```Custom``` action, you need to check whether the ```LowerOperation``` function can support for the operation.
3. Modified like the function ```LowerVECTOR_SHUFFLE``` to generate new node for the specific masks.
In some cases, need to change the ```assertions```.

Others
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I just rewrite a ```VR32``` for ```v32i1``` instead of using ```GR32``` directly, so that the ```def : Pat <(i32 (bitconvert (v32i1 VR32:$src))), (i32 VR32:$src)>;``` can be compiled successfully.